公开(公告)号：US07989882B2

公开(公告)日：2011-08-02

申请号：US11952447

申请日：2007-12-07

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US20100289032A1

公开(公告)日：2010-11-18

申请号：US12719497

申请日：2010-03-08

申请人： Qingchun Zhang ,  Anant K. Agarwal ,  Tangali S. Sudarshan ,  Alexander Bolotnikov

发明人： Qingchun Zhang ,  Anant K. Agarwal ,  Tangali S. Sudarshan ,  Alexander Bolotnikov

IPC分类号： H01L29/24 ,  H01L21/225

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L21/223 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/36 ,  H01L29/8613 ,  H01L29/872

摘要： An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm−2.

摘要翻译： 电子器件包括具有第一导电类型的碳化硅层和邻近碳化硅层的表面的主结，以及邻近主结的碳化硅层表面处的结终端区。 连接终端区域中的电荷随着与主结的横向距离而减小，并且接合终端区域中的最大电荷可能小于约2×1014cm-2。

公开(公告)号：US07728402B2

公开(公告)日：2010-06-01

申请号：US11496842

申请日：2006-08-01

申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.

摘要翻译： 半导体器件包括具有第一导电类型的半导体层，半导体层上的金属接触并与半导体层形成肖特基结，以及半导体层中的半导体区域。 半导体区域和半导体层与肖特基结并联形成第一p-n结。 第一p-n结被配置为当肖特基结被反向偏置时在与肖特基结相邻的半导体层中产生耗尽区，从而限制通过肖特基结的反向漏电流。 第一p-n结进一步配置成使得当肖特基结被反向偏置时，第一p-n结的穿通以比肖特基结的击穿电压低的电压发生。

公开(公告)号：US20090289262A1

公开(公告)日：2009-11-26

申请号：US12124341

申请日：2008-05-21

申请人： Qingchun Zhang ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  Sei-Hyung Ryu

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/872 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/861

摘要： An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

摘要翻译： 电子器件包括具有第一导电类型的碳化硅漂移区，漂移区上的肖特基接触以及与肖特基接触相邻的漂移区的表面处的多个接合势垒肖特基（JBS）区。 JBS区域具有与第一导电类型相反的第二导电类型，并且在相邻的JBS区域之间具有第一间隔。 该装置还包括具有第二导电类型的多个浪涌保护子区域。 浪涌保护子区域中的每一个在相邻的浪涌保护子区域之间具有小于第一间隔的第二间隔。

公开(公告)号：US20090072242A1

公开(公告)日：2009-03-19

申请号：US11857037

申请日：2007-09-18

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L29/739 ,  H01L21/331 ,  H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/0603 ,  H01L29/66068 ,  H01L29/7395

摘要： Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

摘要翻译： 提供绝缘栅双极型导电晶体管（IBCT）。 IBCT包括具有第一导电类型的漂移层。 发射极阱区设置在漂移层中，并且具有与第一导电类型相反的第二导电类型。 阱区设置在漂移层中并且具有第二导电类型。 阱区域与发射极阱区域间隔开。 发射极阱区和阱区之间的空间限定了IBCT的JFET区。 发射极区域设置在阱区中并且具有第一导电类型，并且在发射极阱区，阱区和JFET区上设置掩埋沟道层并具有第一导电类型。 还提供了相关的制造方法。

公开(公告)号：US20080296771A1

公开(公告)日：2008-12-04

申请号：US11756020

申请日：2007-05-31

申请人： Mrinal Kanti Das ,  Qingchun Zhang ,  John M. Clayton, JR. ,  Matthew Donofrio

发明人： Mrinal Kanti Das ,  Qingchun Zhang ,  John M. Clayton, JR. ,  Matthew Donofrio

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L29/66068 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/268 ,  H01L23/4827 ,  H01L29/1095 ,  H01L29/7395 ,  H01L2224/04026 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.

摘要翻译： 通过在n型碳化硅衬底上形成p型碳化硅外延层并在p型碳化硅外延层上形成碳化硅功率器件结构来制造碳化硅功率器件。 至少部分去除n型碳化硅衬底，以露出p型碳化硅外延层。 在露出的至少一些p型碳化硅外延层上形成欧姆接触。 通过至少部分去除n型碳化硅衬底并在p型碳化硅外延层上形成欧姆接触，可以减少或消除使用p型衬底的缺点。 还描述了相关结构。

公开(公告)号：US06475520B1

公开(公告)日：2002-11-05

申请号：US09787338

申请日：2001-03-16

申请人： Wanhui Liu ,  Qingchun Zhang ,  Shixu Li ,  Kajia Su ,  Shuyan Liu ,  Fabing Zhu

发明人： Wanhui Liu ,  Qingchun Zhang ,  Shixu Li ,  Kajia Su ,  Shuyan Liu ,  Fabing Zhu

IPC分类号： A61K920

CPC分类号： C07J53/00 ,  A61K31/56 ,  A61K31/70 ,  C07J63/00

摘要： The present invention relates to a pharmaceutical composition with low toxicity for anti-inflammatory and anti-exudative which contains as active ingredients escin with general formula I and escin with general formula II as well as pharmaceutically acceptable carrier or excipient. In comparison with ESCIN, this pharmaceutical composition possesses the same anti-inflammatory and anti-exudative activity, but both toxicity and irritation lower remarkably.

摘要翻译： 本发明涉及具有低抗毒性和抗渗透性的药物组合物，其含有通式Ⅰ的活性成分和通式II的七叶素以及药学上可接受的载体或赋形剂。 与ESCIN相比，该药物组合物具有相同的抗炎和抗渗血作用，但毒性和刺激性明显降低。

公开(公告)号：US09601605B2

公开(公告)日：2017-03-21

申请号：US13438902

申请日：2012-04-04

申请人： Qingchun Zhang ,  Anant K. Agarwal ,  Lin Cheng

发明人： Qingchun Zhang ,  Anant K. Agarwal ,  Lin Cheng

IPC分类号： H01L29/73 ,  H01L29/06 ,  H01L29/74 ,  H01L29/16

CPC分类号： H01L29/7302 ,  H01L29/0626 ,  H01L29/1608 ,  H01L29/7424

摘要： A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.

公开(公告)号：US09171977B2

公开(公告)日：2015-10-27

申请号：US13461049

申请日：2012-05-01

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L31/111 ,  H01L31/0312 ,  H01L27/144 ,  H01L29/74 ,  H01L29/16

CPC分类号： H01L31/1113 ,  H01L27/1443 ,  H01L29/1608 ,  H01L29/7428 ,  H01L31/0312

摘要： A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced.

摘要翻译： 晶闸管包括第一导电型半导体层，半导体层上的第一导电型载流子注入层，载流子注入层上的第二导电型漂移层，漂移层上的第一导电型基极层和第二导电型 阳极区域。 选择载流子注入层的厚度和掺杂浓度以响应于晶闸管的工作温度的升高来减少载流子注入层的少数载流子注入。 因此，晶闸管从正向电压的负温度系数向正向电压的正温度系数偏移的交叉电流密度降低。

公开(公告)号：US08835987B2

公开(公告)日：2014-09-16

申请号：US11711383

申请日：2007-02-27

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/739 ,  H01L29/16

CPC分类号： H01L29/36 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/7393 ,  H01L29/7395

摘要： An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.

摘要翻译： 绝缘栅双极晶体管（IGBT）在基板上包括第一导电型基板和第二导电型漂移层。 第二导电类型与第一导电类型相反。 IGBT还包括漂移层上的电流抑制层。 电流抑制层具有第二导电类型并且具有大于漂移层的掺杂浓度的掺杂浓度。 第一导电型阱区在电流抑制层中。 阱区具有小于电流抑制层的厚度的结深度，并且电流抑制层横向延伸在阱区之下。 第二导电类型的发射极区域在阱区中。