BIPOLAR JUNCTION TRANSISTOR WITH IMPROVED AVALANCHE CAPABILITY
    1.
    发明申请
    BIPOLAR JUNCTION TRANSISTOR WITH IMPROVED AVALANCHE CAPABILITY 有权
    具有改进的AVALANCHE能力的双极连接晶体管

    公开(公告)号:US20130264581A1

    公开(公告)日:2013-10-10

    申请号:US13438902

    申请日:2012-04-04

    IPC分类号: H01L29/73

    摘要: A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.

    摘要翻译: 公开了一种双极结型晶体管(BJT),其包括集电极层,集电极层上的基极层,基极层上的发射极层,以及埋设在集电极层中的凹陷区域。 基极集电体平面位于基极层和集电极层之间。 凹陷区域可以在底部 - 集电极平面之下。 此外,凹部区域和基底层是第一种类型的半导体材料。 通过将凹部嵌入集电极层中,凹陷区域和集电极层形成第一P-N结,其可以为BJT提供雪崩点。 此外,集电极层和基极层形成第二P-N结。 通过将雪崩点与第二P-N结分开,BJT可能会强烈地雪崩,从而降低雪崩诱发故障的可能性,特别是在碳化硅(SiC)BJT中。

    Bipolar junction transistor with improved avalanche capability

    公开(公告)号:US09601605B2

    公开(公告)日:2017-03-21

    申请号:US13438902

    申请日:2012-04-04

    摘要: A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.

    High-gain wide bandgap darlington transistors and related methods of fabrication
    3.
    发明授权
    High-gain wide bandgap darlington transistors and related methods of fabrication 有权
    高增益宽带隙达林顿晶体管及相关制造方法

    公开(公告)号:US09478537B2

    公开(公告)日:2016-10-25

    申请号:US12503386

    申请日:2009-07-15

    摘要: A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.

    摘要翻译: 封装的功率电子器件包括具有基极,集电极和发射极端子的宽带隙双极驱动晶体管,以及具有基极,集电极和发射极端子的宽带隙双极性输出晶体管。 输出晶体管的集电极端子耦合到驱动晶体管的集电极端子,并且输出晶体管的基极端子耦合到驱动晶体管的发射极端子以提供达林顿对。 在平面图中,输出晶体管的面积比驱动晶体管的面积至少大3倍。 例如,输出晶体管与驱动晶体管的面积比可以在约3:1至约5:1之间。 还讨论了相关装置和制造方法。

    Power Switching Devices Having Controllable Surge Current Capabilities
    9.
    发明申请
    Power Switching Devices Having Controllable Surge Current Capabilities 有权
    具有可控浪涌电流能力的电源开关器件

    公开(公告)号:US20100301929A1

    公开(公告)日:2010-12-02

    申请号:US12610582

    申请日:2009-11-02

    IPC分类号: H01L25/00 H01L29/24

    摘要: Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide hand-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.

    摘要翻译: 半导体开关器件包括宽带隙功率晶体管,与功率晶体管并联耦合的宽带隙浪涌电流晶体管,以及配置为驱动浪涌电流晶体管的宽手持式驱动晶体管。 当功率晶体管的漏极 - 源极电压处于第一电压范围内时,半导体开关器件的大部分导通状态输出电流流过功率晶体管的沟道,该范围可以例如对应于漏极 在正常运行期间预期的电源电压。 相比之下,半导体开关器件被进一步配置成使得在导通状态下,当功率晶体管的漏 - 源电压在一秒内时,输出电流流过功率晶体管的浪涌电流晶体管和沟道, 电压范围

    High power insulated gate bipolar transistors
    10.
    发明授权
    High power insulated gate bipolar transistors 有权
    大功率绝缘栅双极晶体管

    公开(公告)号:US08710510B2

    公开(公告)日:2014-04-29

    申请号:US11764492

    申请日:2007-06-18

    IPC分类号: H01L31/0312

    摘要: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

    摘要翻译: 绝缘栅双极晶体管(IGBT)包括具有第一导电类型的衬底,具有与第一导电类型相反的第二导电类型的漂移层以及漂移层中具有第一导电类型的阱区。 外延沟道调整层位于漂移层上,具有第二导电类型。 发射极区从外延沟道调节层的表面延伸穿过外延沟道调节层并进入阱区。 发射极区域具有第二导电类型,并且至少部分地限定与发射极区域相邻的阱区域中的沟道区域。 栅极氧化层位于沟道区上,栅极位于栅极氧化层上。 还公开了相关方法。