公开(公告)号：US06620676B2

公开(公告)日：2003-09-16

申请号：US09895672

申请日：2001-06-29

申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

公开(公告)号：US06605838B1

公开(公告)日：2003-08-12

申请号：US10261219

申请日：2002-09-30

申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Gerd Fehlauer ,  Stephan Kudelka ,  Uwe Schroeder ,  Helmut H. Tews

发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Gerd Fehlauer ,  Stephan Kudelka ,  Uwe Schroeder ,  Helmut H. Tews

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10864 ,  H01L29/66181 ,  H01L29/945

摘要： A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

摘要翻译： 提供了沟槽电容器存储单元结构，其包括垂直轴环区域，其抑制存在于垂直MOSFET和下面的沟槽电容器之间的相邻垂直寄生晶体管的电流泄漏。 具有约0.50μm或更小的垂直长度的垂直环形隔离件包括部分在沟槽外部存在的第一部分和存在于沟槽内部的第二部分。 轴环氧化物的第一部分比所述第二部分氧化物厚，从而减少了寄生电流泄漏。

公开(公告)号：US06566228B1

公开(公告)日：2003-05-20

申请号：US10083744

申请日：2002-02-26

申请人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

发明人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/763 ,  H01L27/1052

摘要： Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

摘要翻译： 公开了一种同时提供用于由衬底材料制成的半导体衬底的阵列和支撑区域的沟槽隔离的方法，所述方法包括提供用于阵列和支撑区域的第一硬掩模层，所述第一硬掩模包括限定沟槽隔离的掩模开口 在阵列和支撑区域中，在阵列区域中提供深阵列沟槽隔离，在足以填充所述掩模开口和深阵列沟槽隔离的支撑和阵列区域上提供覆盖的平面化导电材料层，通过所述第一硬 掩模材料下降到所述半导体衬底中，以便形成支撑沟槽隔离，使得深阵列沟槽隔离和支撑沟槽隔离都具有相同的深度，并且其中包括一定数量的所述导电材料的导电元件保留在 每个所述深阵列沟槽。

公开(公告)号：US06429477B1

公开(公告)日：2002-08-06

申请号：US09702315

申请日：2000-10-31

申请人： Jack A. Mandelman ,  Rama Divakaruni ,  William R. Tonti

发明人： Jack A. Mandelman ,  Rama Divakaruni ,  William R. Tonti

IPC分类号： H01L2976

CPC分类号： H01L27/10861 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10888 ,  H01L27/1203

摘要： The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity. Additionally, the shared via body contact and diffusion contact can be selectively formed borderless to adjacent gate conductors in the device.

摘要翻译： 优选实施例通过提供在用于绝缘体上硅（SOI）技术的单个共享通孔中形成的体接触和扩散接触来克服背景技术中发现的困难。 通过在单个共享通孔中形成体接触和扩散接触，器件尺寸最小化并且性能得到改善。 特别地，形成的体接触将SOI层与底层衬底连接，以避免由浮动SOI沟道区产生的不稳定性和漏电。 形成的扩散触点将器件扩散连接到上述布线以便于器件操作。 通过在单个共享通孔中将身体接触和扩散接触提供在一起，优选的实施例避免了由单独接触引起的区域损失。 此外，优选实施例提供与其他装置自对准的身体接触，使尽可能少的过程复杂性所需的公差最小化。 此外，共享的通孔体接触和扩散接触可以选择性地形成与设备中的相邻栅极导体无边界。

公开(公告)号：US07425754B2

公开(公告)日：2008-09-16

申请号：US10708340

申请日：2004-02-25

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

IPC分类号： H01L27/102

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

公开(公告)号：US07265417B2

公开(公告)日：2007-09-04

申请号：US10867772

申请日：2004-06-16

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US20070096259A1

公开(公告)日：2007-05-03

申请号：US11633380

申请日：2006-12-04

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.

摘要翻译： 提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。 外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。 低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。 形成发射极层以覆盖本征基极层。

公开(公告)号：US20050260801A1

公开(公告)日：2005-11-24

申请号：US10996866

申请日：2004-11-24

申请人： Rama Divakaruni ,  Louis Hsu ,  Rajiv Joshi ,  Carl Radens

发明人： Rama Divakaruni ,  Louis Hsu ,  Rajiv Joshi ,  Carl Radens

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US06870211B1

公开(公告)日：2005-03-22

申请号：US10605590

申请日：2003-10-10

申请人： Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

发明人： Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

IPC分类号： H01L21/60 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

摘要翻译： 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

公开(公告)号：US20050059214A1

公开(公告)日：2005-03-17

申请号：US10605227

申请日：2003-09-16

申请人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Rama Divakaruni ,  Oleg Gluschenkov

发明人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Rama Divakaruni ,  Oleg Gluschenkov

IPC分类号： H01L21/8242 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

摘要： A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces resistance on the bitline contact.

摘要翻译： SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，从多沟槽填充中去除空隙并降低位线接触的电阻。