公开(公告)号：US06842813B1

公开(公告)日：2005-01-11

申请号：US09591928

申请日：2000-06-12

申请人： Randy B. Osborne ,  David J. Harriman

发明人： Randy B. Osborne ,  David J. Harriman

IPC分类号： G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4273

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a first agent, a point to point half duplex interface coupled to the first agent and a second agent coupled to the first point to point half duplex interface. The first agent is adaptable to transmit a signal to the second agent via a first component of the interface indicating the type of data traffic to be transmitted to the second agent.

摘要翻译： 根据一个实施例，公开了一种计算机系统。 计算机系统包括第一代理，耦合到第一代理的点对点半双工接口和耦合到第一点到点半双工接口的第二代理。 第一代理适用于经由接口的第一组件向第二代理发送信号，指示要发送给第二代理的数据流量的类型。

公开(公告)号：US06256697B1

公开(公告)日：2001-07-03

申请号：US09223638

申请日：1998-12-30

申请人： Jasmin Ajanovic ,  David J. Harriman

发明人： Jasmin Ajanovic ,  David J. Harriman

IPC分类号： G06F1336

CPC分类号： G06F13/36

摘要： An apparatus for reusing arbitration signals to frame data transfers between hub agents is disclosed. The apparatus includes an arbitration signal output circuit to output a first request signal to indicate a data transfer. The apparatus further includes a data path input/output unit to output data to a data path during a period indicated by the arbitration signal.

摘要翻译： 公开了一种用于重用仲裁信号以组合集线器代理之间的数据传输的装置。 该装置包括仲裁信号输出电路，用于输出第一请求信号以指示数据传送。 该装置还包括数据路径输入/输出单元，用于在由仲裁信号指示的时段期间向数据路径输出数据。

公开(公告)号：US6092158A

公开(公告)日：2000-07-18

申请号：US874414

申请日：1997-06-13

申请人： David J. Harriman ,  Brian K. Langendorf ,  Jasmin Ajanovic

发明人： David J. Harriman ,  Brian K. Langendorf ,  Jasmin Ajanovic

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1642

摘要： A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command queue block having a plurality of command queues, each being coupled to receive a different type of command. The memory controller also includes arbitration logic which, among other things, selects high priority read commands before high priority write commands. Memory interface logic generates memory accesses performing commands selected by the arbitration logic.

摘要翻译： 一种用于在命令流之间进行仲裁的方法和装置。 该方法解除阻塞的高优先级命令，然后选择剩余的高优先级命令。 在优先级高的命令之后选择正常优先级命令。 所描述的存储器控​​制器包括具有多个命令队列的命令队列块，每个命令队列被耦合以接收不同类型的命令。 存储器控制器还包括仲裁逻辑，其中除了别的以外，在高优先级写入命令之前选择高优先级的读取命令。 存储器接口逻辑产生执行由仲裁逻辑选择的命令的存储器访问。

公开(公告)号：US20190052617A1

公开(公告)日：2019-02-14

申请号：US16024469

申请日：2018-06-29

申请人： Yu-Yuan Chen ,  Wojciech S. Powiertowski ,  Srikanth Varadarajan ,  David J. Harriman

发明人： Yu-Yuan Chen ,  Wojciech S. Powiertowski ,  Srikanth Varadarajan ,  David J. Harriman

IPC分类号： H04L29/06 ,  H04L9/08 ,  G06F13/42

摘要： A device includes a microcontroller, memory including secure memory to store a private key, a set of registers, and an authentication engine. The set of registers includes a write mailbox register and a read mailbox register, and message data is to be written to the write mailbox register by a host system. The message data includes at least a portion of a challenge request, and the challenge request includes a challenge by the host system to authenticity of the device. The authentication engine generates a response to the challenge, where the response includes data to identify attributes of the device and a signature generated using the private key. The authentication engine causes at least a portion of the response to be written to the read mailbox register to be read by the host system.

公开(公告)号：US20150117504A1

公开(公告)日：2015-04-30

申请号：US14126926

申请日：2013-10-30

申请人： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

发明人： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

IPC分类号： H04B17/00

CPC分类号： G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

摘要： In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

公开(公告)号：US20140281062A1

公开(公告)日：2014-09-18

申请号：US13844323

申请日：2013-03-15

申请人： David J. Harriman ,  Annie Foong ,  Debendra Das Sharma

发明人： David J. Harriman ,  Annie Foong ,  Debendra Das Sharma

IPC分类号： G06F13/42

CPC分类号： G06F13/423 ,  G06F3/067 ,  G06F9/44 ,  G06F9/4411 ,  G06F13/385 ,  H04L63/08

摘要： Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another.

摘要翻译： 提供使用输入/输出（I / O）设备访问功能的技术和机制。 在一个实施例中，包括I / O设备的计算机系统的主存储器存储将功能与用于访问功能的上下文相关联的功能上下文数据结构。 I / O设备存储I / O设备的配置以提供功能。 在另一个实施例中，软件过程与功能上下文数据结构交换信息以访问功能。 I / O设备相对于彼此执行功能上下文数据结构和配置数据结构的同步，其中功能上下文数据结构作为将I / O设备和软件过程接口的寄存器级接口 彼此之间。

公开(公告)号：US08806258B2

公开(公告)日：2014-08-12

申请号：US12286544

申请日：2008-09-30

申请人： Seh W. Kwa ,  Neil Songer ,  Rob Gough ,  David J. Harriman

发明人： Seh W. Kwa ,  Neil Songer ,  Rob Gough ,  David J. Harriman

IPC分类号： G06F1/12

CPC分类号： G06F1/324 ,  G06F1/3209 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4265 ,  Y02B60/1235 ,  Y02D10/151

摘要： A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

摘要翻译： 在一些实施例中，可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备，并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段，而且活动的断言是有利的，因为主机芯片组已经从 降低功耗状态。

公开(公告)号：US08782321B2

公开(公告)日：2014-07-15

申请号：US13369140

申请日：2012-02-08

申请人： David J. Harriman ,  Maxim Dan

发明人： David J. Harriman ,  Maxim Dan

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/387 ,  G06F13/4295 ,  G06F2213/0026

摘要： Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

摘要翻译： 描述了跨计算机设备的多协议I / O互连的PCIe隧道的方法，装置和系统的实施例。 跨多协议I / O互连的PCIe隧道的方法可以包括在计算机设备的多协议I / O互连的交换结构的端口之间建立第一通信路径，以响应于外围组件互连express（PCIe ）设备连接到计算机设备，并且在交换结构和PCIe控制器之间建立第二通信路径。 该方法还可以包括通过多协议I / O互连，通过第一和第二通信路径将PCIe设备的PCIe协议分组从PCIe设备路由到PCIe控制器。 可以描述和要求保护其他实施例。

公开(公告)号：US20140173164A1

公开(公告)日：2014-06-19

申请号：US14186677

申请日：2014-02-21

申请人： Sridharan Ranganathan ,  Mahesh Wagh ,  David J. Harriman

发明人： Sridharan Ranganathan ,  Mahesh Wagh ,  David J. Harriman

IPC分类号： G06F13/38

CPC分类号： G06F13/385 ,  G06F13/40 ,  H04L49/109

摘要： In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供跨物理互连的数据传输。 该堆叠可以并入包括用于包括交易和链路层的第一通信协议的协议栈的装置，以及耦合到协议栈的物理（PHY）单元，以在设备和耦合到装置的设备之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

公开(公告)号：US20130132683A1

公开(公告)日：2013-05-23

申请号：US13713614

申请日：2012-12-13

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.