公开(公告)号：US11776615B2

公开(公告)日：2023-10-03

申请号：US17673302

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

IPC: G11C11/408 ,  G06F12/02 ,  G11C11/4074

CPC classification number: G11C11/4087 ,  G06F12/0246 ,  G11C11/4074 ,  G11C11/4085 ,  G06F2212/7201

Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.

公开(公告)号：US11735269B2

公开(公告)日：2023-08-22

申请号：US17589172

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C8/00 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3445 ,  G11C11/5671 ,  G11C16/3409 ,  H10B41/27 ,  H10B43/27

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US11709771B2

公开(公告)日：2023-07-25

申请号：US17739578

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  H04L9/06 ,  H04L9/08 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  G11C11/5628 ,  H04L9/0662 ,  H04L9/0869 ,  G06F2212/7207

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US11693586B2

公开(公告)日：2023-07-04

申请号：US17357496

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246

Abstract: The present disclosure relates to designating or allocating static and dynamic SLC blocks between a non-write burst free block pool and a write burst free block pool. In some embodiments, a free block pool can be utilized by a host for write burst operations and/or non-write burst operations. In these embodiments, the over provisioning portion of the memory sub-system can be designated into a plurality of portions.

公开(公告)号：US11635899B2

公开(公告)日：2023-04-25

申请号：US17573224

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/02

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

公开(公告)号：US11593032B1

公开(公告)日：2023-02-28

申请号：US17395695

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US11567682B2

公开(公告)日：2023-01-31

申请号：US16685300

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Ankit Vinod Vashi ,  Xiangang Luo ,  Jianmin Huang

IPC: G06F3/06

Abstract: Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.

公开(公告)号：US20220342829A1

公开(公告)日：2022-10-27

申请号：US17859963

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F12/1009 ,  G06F11/10

Abstract: A logical to physical (L2P) mapping component can determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both. The L2P mapping component can further cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both.

公开(公告)号：US11436078B2

公开(公告)日：2022-09-06

申请号：US17228425

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Jianmin Huang ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/419 ,  G06F12/02

Abstract: Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

公开(公告)号：US20220229574A1

公开(公告)日：2022-07-21

申请号：US17647943

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jianmin Huang

IPC: G06F3/06

Abstract: Methods, systems, and devices for data migration techniques are described. The memory system may receive a command associated with a write operation from a host device. The memory system may determine whether to use a data migration technique for writing data to the memory device based on receiving the command. In some cases, the memory system may select a tri-level write format instead of a quad-level write format for writing the data and write the data using the tri-level write format. The memory system may convert the data from the tri-level write format to the quad-level write format based on writing the data using the tri-level write format.