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    FABRICATION OF ELECTRODES FOR MEMORY CELLS
    31.
    发明申请
    FABRICATION OF ELECTRODES FOR MEMORY CELLS 有权

    公开(公告)号：US20210098697A1

    公开(公告)日：2021-04-01

    申请号：US17066409

    申请日：2020-10-08

    Applicant: Micron Technology, Inc.

    Inventor： Pengyuan Zheng ,  Yongjun J. Hu ,  Yao Jin ,  Hongqi Li ,  Andrea Gotti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

    Techniques for forming memory structures
    32.
    发明授权
    Techniques for forming memory structures 有权

    公开(公告)号：US10930849B2

    公开(公告)日：2021-02-23

    申请号：US16456349

    申请日：2019-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  Pavan Reddy K. Aella ,  Dale W. Collins

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

    Fabrication of electrodes for memory cells
    33.
    发明授权
    Fabrication of electrodes for memory cells 有权

    公开(公告)号：US10825987B2

    公开(公告)日：2020-11-03

    申请号：US16001795

    申请日：2018-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Pengyuan Zheng ,  Yongjun J. Hu ,  Yao Jin ,  Hongqi Li ,  Andrea Gotti

    IPC: H01L21/28 ,  H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

    SEMICONDUCTOR DEVICES INCLUDING LINERS, AND RELATED SYSTEMS
    34.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING LINERS, AND RELATED SYSTEMS 审中-公开

    公开(公告)号：US20190097133A1

    公开(公告)日：2019-03-28

    申请号：US16202379

    申请日：2018-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

    Structures incorporating and methods of forming metal lines including carbon
    35.
    发明授权
    Structures incorporating and methods of forming metal lines including carbon 有权

    公开(公告)号：US10153428B2

    公开(公告)日：2018-12-11

    申请号：US15473338

    申请日：2017-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Innocenzo Tortorelli ,  Enrico Varesi

    IPC: H01L45/00 ,  H01L27/24 ,  H01L27/22

    Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

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