公开(公告)号：US10546848B2

公开(公告)日：2020-01-28

申请号：US16398433

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

IPC: G11C11/34 ,  H01L27/02 ,  H01L21/82 ,  H01L27/12 ,  G11C5/06 ,  H01L23/532

Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10355014B1

公开(公告)日：2019-07-16

申请号：US15852989

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US12171101B2

公开(公告)日：2024-12-17

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/49 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/30 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230380172A1

公开(公告)日：2023-11-23

申请号：US17748924

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee ,  Daniel Billingsley ,  Alyssa N. Scarbrough

IPC: H01L27/11573 ,  H01L27/11529

CPC classification number: H01L27/11573 ,  H01L27/11529

Abstract: Methods, systems, and devices for a barrier structure for preventing removal of, such as etching to, control circuitry are described. A memory device may include control circuitry over a substrate and for accessing a memory array and contact regions configured to couple with the control circuitry. The memory device may include barrier regions between respective contact regions that includes a barrier material. The memory device may include a stack of layers over the barrier region and the contact regions that is associated with the memory array, and the barrier material may prevent a removal (e.g., an etch) through the stack of layers and at least partially between contact regions from extending to the control circuitry.

公开(公告)号：US20230099418A1

公开(公告)日：2023-03-30

申请号：US18076702

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  G11C16/04

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230016742A1

公开(公告)日：2023-01-19

申请号：US17375602

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  Yongjun Jeff Hu ,  Rita J. Klein ,  Everett A. McTeer

IPC: H01L29/51 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

Abstract: Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoOxNy, where each of “x” and “y” is from 0 to 4.0; and (b): MoMz, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers. The memory cells individually comprise the channel material of individual of the channel-material strings, the storage material, the at least one of AlOq, ZrOq, and HfOq, the at least one of the (a) and the (b), and the metal material. Other embodiments are disclosed.

公开(公告)号：US11527546B2

公开(公告)日：2022-12-13

申请号：US16943826

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11529

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11315877B2

公开(公告)日：2022-04-26

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20220068945A1

公开(公告)日：2022-03-03

申请号：US17068470

申请日：2020-10-12

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

IPC: H01L27/11556 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220037350A1

公开(公告)日：2022-02-03

申请号：US16943826

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L29/49 ,  H01L21/28

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.