公开(公告)号：US20170365322A1

公开(公告)日：2017-12-21

申请号：US15692994

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US09792973B2

公开(公告)日：2017-10-17

申请号：US15073989

申请日：2016-03-18

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

公开(公告)号：US20170256300A1

公开(公告)日：2017-09-07

申请号：US15057914

申请日：2016-03-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US09734886B1

公开(公告)日：2017-08-15

申请号：US15012566

申请日：2016-02-01

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US20250130908A1

公开(公告)日：2025-04-24

申请号：US18937428

申请日：2024-11-05

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/20 ,  G06F11/10 ,  G06F11/14 ,  G11C11/22 ,  G11C29/12 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US20230148359A1

公开(公告)日：2023-05-11

申请号：US18048738

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/221

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

公开(公告)号：US11501815B2

公开(公告)日：2022-11-15

申请号：US17171873

申请日：2021-02-09

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim ,  Scott James Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

公开(公告)号：US11127450B2

公开(公告)日：2021-09-21

申请号：US17064116

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.

公开(公告)号：US11056165B2

公开(公告)日：2021-07-06

申请号：US16893304

申请日：2020-06-04

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US10950286B2

公开(公告)日：2021-03-16

申请号：US16733160

申请日：2020-01-02

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C5/10 ,  G11C5/06 ,  G11C11/22 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/11507 ,  H01L23/528 ,  G11C11/408 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  H01L27/11509

Abstract: Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.