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    Cross-point memory array and related fabrication techniques
    31.
    发明授权
    Cross-point memory array and related fabrication techniques 有权

    公开(公告)号：US10825867B2

    公开(公告)日：2020-11-03

    申请号：US15961540

    申请日：2018-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

    IPC: H01L27/24 ,  H01L27/11514 ,  H01L45/00

    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

    BURIED LINES AND RELATED FABRICATION TECHNIQUES
    32.
    发明申请
    BURIED LINES AND RELATED FABRICATION TECHNIQUES 审中-公开

    公开(公告)号：US20200323083A1

    公开(公告)日：2020-10-08

    申请号：US16905363

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro ,  Stephen W. Russell ,  Stephen H. Tang

    IPC: H05K3/00 ,  H05K1/11 ,  H05K3/22

    Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

    Buried lines and related fabrication techniques
    33.
    发明授权
    Buried lines and related fabrication techniques 有权

    公开(公告)号：US10729012B2

    公开(公告)日：2020-07-28

    申请号：US15961550

    申请日：2018-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

    IPC: H05K3/00 ,  H05K1/11 ,  H05K3/22

    Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

    Array of cross point memory cells and methods of forming an array of cross point memory cells
    35.
    发明授权
    Array of cross point memory cells and methods of forming an array of cross point memory cells 有权

    公开(公告)号：US10424618B2

    公开(公告)日：2019-09-24

    申请号：US15851112

    申请日：2017-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Stephen W. Russell ,  Tony M. Lindenberg

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

    Array of cross point memory cells and methods of forming an array of cross point memory cells
    37.
    发明授权
    Array of cross point memory cells and methods of forming an array of cross point memory cells 有权
    交叉点存储单元阵列和形成交叉点存储单元阵列的方法

    公开(公告)号：US09362494B2

    公开(公告)日：2016-06-07

    申请号：US14293577

    申请日：2014-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Stephen W. Russell ,  Tony M. Lindenberg

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2472 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

    Abstract translation: 交叉点存储单元的阵列包括间隔开的内部第一线，与第一线交叉的间隔开的外部第二直线，以及在第一和第二线之间的高阻状态区域，这样的交叉。 多电阻状态区域的个体包括彼此电耦合的高度外部的多重电阻状态材料和正向内部多电阻状态材料。 内部多阻态材料具有垂直横截面中的相对边缘。 外部多阻态材料在垂直横截面中具有相对于内部多阻态材料的相对边缘在垂直横截面中横向偏移的相对边缘。 还公开了方法。

    Memory cells and methods of forming memory cells
    38.
    发明授权
    Memory cells and methods of forming memory cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US09324945B2

    公开(公告)日：2016-04-26

    申请号：US13959958

    申请日：2013-08-06

    Applicant: Micron Technology, Inc.

    Inventor： Lequn Jennifer Liu ,  Stephen W. Russell ,  Fabio Pellizzer ,  Swapnil Lengade

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/165 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1675

    Abstract: A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. Protective material is formed elevationally over the outer electrode material. Dopant is implanted through the protective material into the outer electrode material and the programmable material and across the interface to enhance adhesion of the outer electrode material and the programmable material relative one another across the interface. Memory cells are also disclosed.

    Abstract translation: 一种形成存储单元的方法包括在外部电极材料上形成并且直接抵靠可编程材料。 可编程材料和外部电极材料沿着界面彼此接触。 保护材料在外部电极材料上垂直地形成。 通过保护材料将掺杂剂注入到外部电极材料和可编程材料中并跨越界面，以增强外部电极材料和可编程材料相对于界面的粘合性。 还公开了存储单元。

    Sparse piers for three-dimensional memory arrays
    40.
    发明授权
    Sparse piers for three-dimensional memory arrays 有权

    公开(公告)号：US12302766B2

    公开(公告)日：2025-05-13

    申请号：US17656280

    申请日：2022-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Enrico Varesi ,  David H. Wells ,  Paolo Fantini ,  Lorenzo Fratin

    IPC: H10B63/10 ,  G11C13/00 ,  H10B63/00 ,  H10D64/01 ,  H10N70/00 ,  H01L21/02

    Abstract: Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

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