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1.发明授权公开(公告)号：US11768603B2
公开(公告)日：2023-09-26
申请号：US17662100
申请日：2022-05-05
Applicant: Micron Technology, Inc.
Inventor： Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
CPC classification number: G06F3/061 , G06F3/0644 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G11C7/1042 , G11C7/1045 , G11C8/12 , G11C16/08
Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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公开(公告)号：US20190013358A1
公开(公告)日：2019-01-10
申请号：US16045514
申请日：2018-07-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jong-Won Lee , Gianpaolo Spadini , Stephen W. Russell , Derchang Kau
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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公开(公告)号：US09659997B2
公开(公告)日：2017-05-23
申请号：US15058810
申请日：2016-03-02
Applicant: Micron Technology, Inc.
Inventor： Jong-Won Lee , Gianpaolo Spadini , Stephen W. Russell , Derchang Kau
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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公开(公告)号：US20150280118A1
公开(公告)日：2015-10-01
申请号：US14228104
申请日：2014-03-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jong-Won Lee , Gianpaolo Spadini , Stephen W. Russell , Derchang Kau
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
Abstract translation: 公开了形成包含相变和/或硫族化物材料的记忆单元的方法。 在一个方面，该方法包括提供沿第一方向延伸的下线叠层，下线叠层包括在下导电线上的牺牲线。 该方法还包括通过选择性地去除牺牲线的牺牲材料并用硫族化物材料代替牺牲线来形成沿第一方向延伸的硫属化物线。
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公开(公告)号：US20200279889A1
公开(公告)日：2020-09-03
申请号：US16877166
申请日：2020-05-18
Applicant: Micron Technology, Inc.
Inventor： Jong Lee , Gianpaolo Spadini , Derchang Kau
Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.
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Patent Agency Ranking
公开(公告)号：US10475853B2
公开(公告)日：2019-11-12
申请号：US16045514
申请日：2018-07-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jong-Won Lee , Gianpaolo Spadini , Stephen W. Russell , Derchang Kau
Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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公开(公告)号：US10050084B2
公开(公告)日：2018-08-14
申请号：US15481208
申请日：2017-04-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jong-Won Lee , Gianpaolo Spadini , Stephen W. Russell , Derchang Kau
Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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公开(公告)号：US09306165B2
公开(公告)日：2016-04-05
申请号：US14228104
申请日：2014-03-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jong-Won Lee , Gianpaolo Spadini , Stephen W. Russell , Derchang Kau
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
Abstract translation: 公开了形成包含相变和/或硫族化物材料的记忆单元的方法。 在一个方面，该方法包括提供沿第一方向延伸的下线叠层，下线叠层包括在下导电线上的牺牲线。 该方法还包括通过选择性地去除牺牲线的牺牲材料并用硫族化物材料代替牺牲线来形成沿第一方向延伸的硫属化物线。
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9.发明授权公开(公告)号：US11354040B2
公开(公告)日：2022-06-07
申请号：US16926431
申请日：2020-07-10
Applicant: Micron Technology, Inc.
Inventor： Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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10.发明授权公开(公告)号：US10719237B2
公开(公告)日：2020-07-21
申请号：US14992979
申请日：2016-01-11
Applicant: Micron Technology, Inc.
Inventor： Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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