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公开(公告)号：US10937487B2
公开(公告)日：2021-03-02
申请号：US16854239
申请日：2020-04-21
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/24 , G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US10930324B2
公开(公告)日：2021-02-23
申请号：US16877133
申请日：2020-05-18
Applicant: Micron Technology, Inc.
Inventor： Mahdi Jamali , William A. Melton , Daniele Vimercati , Xinwei Guo , Yasuko Hattori
IPC: G11C7/06 , G11C7/08 , G11C11/4091 , G11C11/22
Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
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公开(公告)号：US10672457B2
公开(公告)日：2020-06-02
申请号：US16453208
申请日：2019-06-26
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/24 , G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US20200035292A1
公开(公告)日：2020-01-30
申请号：US16536206
申请日：2019-08-08
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Daniele Vimercati
Abstract: Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.
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公开(公告)号：US10468085B2
公开(公告)日：2019-11-05
申请号：US16105790
申请日：2018-08-20
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Xinwei Guo
Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.
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Patent Agency Ranking
公开(公告)号：US10395718B2
公开(公告)日：2019-08-27
申请号：US16189425
申请日：2018-11-13
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Daniele Vimercati
IPC: G11C11/22
Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
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公开(公告)号：US20190244641A1
公开(公告)日：2019-08-08
申请号：US15892118
申请日：2018-02-08
Applicant: Micron Technology, Inc.
Inventor： Mahdi Jamali , William A. Melton , Daniele Vimercati , Xinwei Guo , Yasuko Hattori
IPC: G11C7/06
CPC classification number: G11C7/065
Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
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公开(公告)号：US09881661B2
公开(公告)日：2018-01-30
申请号：US15173310
申请日：2016-06-03
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Daniele Vimercati
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C11/221 , G11C11/2275
Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
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公开(公告)号：US09245597B2
公开(公告)日：2016-01-26
申请号：US14287946
申请日：2014-05-27
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Mingdong Cui
CPC classification number: G11C13/004 , G05F1/461 , G05F3/16 , G11C5/147 , G11C7/062 , G11C7/14 , G11C8/08 , G11C13/0004 , G11C13/0038 , G11C2013/0054
Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
Abstract translation: 所描述的示例包括用于向感测电路提供参考电压的感测电路和参考电压发生器。 感测电路可以感测可以是PCM存储器单元的存储器单元的状态。 感测电路可以包括共源共栅晶体管。 参考电压发生器的示例可以包括耦合到多个组参考电压发生器的全局参考电压发生器，其可以减小电压发生器路由的输出电阻。
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公开(公告)号：US20140254258A1
公开(公告)日：2014-09-11
申请号：US14287946
申请日：2014-05-27
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Mingdong Cui
CPC classification number: G11C13/004 , G05F1/461 , G05F3/16 , G11C5/147 , G11C7/062 , G11C7/14 , G11C8/08 , G11C13/0004 , G11C13/0038 , G11C2013/0054
Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
Abstract translation: 所描述的示例包括用于向感测电路提供参考电压的感测电路和参考电压发生器。 感测电路可以感测可以是PCM存储器单元的存储器单元的状态。 感测电路可以包括共源共栅晶体管。 参考电压发生器的示例可以包括耦合到多个组参考电压发生器的全局参考电压发生器，其可以减小电压发生器路由的输出电阻。
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