公开(公告)号：US20140054666A1

公开(公告)日：2014-02-27

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L29/788

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US08400831B2

公开(公告)日：2013-03-19

申请号：US12955765

申请日：2010-11-29

申请人： Hoon Cho ,  Kiran Pangal ,  Krishna K. Parat ,  Neal R. Mielke ,  Pranav Kalavade ,  Iwen Chao

发明人： Hoon Cho ,  Kiran Pangal ,  Krishna K. Parat ,  Neal R. Mielke ,  Pranav Kalavade ,  Iwen Chao

IPC分类号： G11C16/04

CPC分类号： G11C16/3495 ,  G11C16/02 ,  G11C16/3404

摘要： A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.

摘要翻译： 一种提高闪存耐久性的方法和装置。 在本发明的一个实施例中，高电场被提供给闪速存储器模块的控制门。 施加到闪速存储器模块的高电场消除了控制栅极和闪存模块的有效区域之间的捕获的电荷。 在本发明的一个实施例中，在闪速存储器模块的擦除操作之前，高电场被施加到闪速存储器模块的控制栅极。 通过将高电场施加到闪速存储器模块的控制栅极，本发明的实施例改善了闪存模块的单级或多级单元的编程/擦除循环衰减。

公开(公告)号：US20120223409A1

公开(公告)日：2012-09-06

申请号：US13471048

申请日：2012-05-14

申请人： Gurtej S. Sandhu ,  Krishna K. Parat

发明人： Gurtej S. Sandhu ,  Krishna K. Parat

IPC分类号： H01L25/065

CPC分类号： H01L23/538 ,  H01L21/76254 ,  H01L21/78 ,  H01L21/8221 ,  H01L23/3185 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

摘要翻译： 公开了在没有电路的受主基板上制造集成电路器件的方法。 集成电路器件通过在接受器衬底上依次布置一个或多个半导体材料层并且在配置下一较高电平之前在每个级别的半导体材料上制造电路而形成。 在封装电路之后，去除受主衬底并切割半导体晶片。 还公开了通过这些方法形成的集成电路器件。

公开(公告)号：US20120153357A1

公开(公告)日：2012-06-21

申请号：US12969975

申请日：2010-12-16

申请人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

发明人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

IPC分类号： H01L23/538 ,  H01L21/82

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

摘要翻译： 简而言之，根据一个或多个实施例，多层存储器设备包括设置在下层甲板上的下甲板和上甲板，甲板包括通过一个或多个触点耦合的一个或多个存储单元。 隔离层设置在上甲板之间，并且在上甲板和下甲板之间形成一个或多个触点，以将上甲板中的一个或多个接触线与下甲板的一个或多个接触线接合。

公开(公告)号：US20110080789A1

公开(公告)日：2011-04-07

申请号：US12573579

申请日：2009-10-05

申请人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

发明人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

摘要翻译： 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。

公开(公告)号：US06570225B2

公开(公告)日：2003-05-27

申请号：US10021543

申请日：2001-10-22

申请人： Krishna K. Parat ,  Neal K. Clark ,  Timothy J. Maloney

发明人： Krishna K. Parat ,  Neal K. Clark ,  Timothy J. Maloney

IPC分类号： H01L2362

CPC分类号： H01L27/0251

摘要： A method includes introducing into an integrated circuit a device comprising a transistor including a drain of a first conductivity type and a first concentration in a well of a first conductivity type and a second concentration, a first region of the first conductivity type and first concentration in the well, and a second region of a second conductivity type in the well between the first region and the drain. The method also includes coupling the device to a pad. In the presence of a pre-determined current at the pad, the device biases a junction between the second region and the well toward current flow in the absence of a latch-up event.

摘要翻译： 一种方法包括向集成电路引入包括晶体管的器件，晶体管包括第一导电类型和第二浓度的阱中的第一导电类型的漏极和第一浓度的第一浓度，第一导电类型的第一区域和第一浓度 以及在第一区域和漏极之间的阱中的第二导电类型的第二区域。 该方法还包括将设备耦合到垫。 在焊盘处存在预定电流的情况下，器件在不存在闩锁事件的情况下，将第二区域和阱之间的接合部朝向电流流动。

公开(公告)号：US5877927A

公开(公告)日：1999-03-02

申请号：US724371

申请日：1996-10-01

申请人： Krishna K. Parat ,  Timothy J. Maloney

发明人： Krishna K. Parat ,  Timothy J. Maloney

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： An arrangement for preventing damage to a circuit of an integrated circuit chip due to the occurrence of voltage introduced externally to the integrated circuit is disclosed. The arrangement generally has a timer circuit, a clamping circuit, and an override circuit. The clamping circuit is coupled between an input and ground such that voltages and currents applied to the input are shunted to ground for a first length of time. The timer circuit is coupled to the input and passes a voltage applied to the input for the first length of time. The output of the timer circuit is disabled at the expiration of the first length of time. The override circuit disables the clamping circuit a second length of time after a power supply voltage exceeds a predetermined level.

摘要翻译： 公开了一种用于防止由于在集成电路外部引入的电压的发生而损坏集成电路芯片的电路的装置。 该装置通常具有定时器电路，钳位电路和超控电路。 钳位电路耦合在输入和地之间，使得施加到输入端的电压和电流在第一时间段内被分流到地。 定时器电路耦合到输入端并传递施加到输入端的电压达一段时间。 定时器电路的输出在第一个时间长度到期时被禁用。 超控电路在电源电压超过预定电平之后将钳位电路禁用第二时间长度。

公开(公告)号：US5731242A

公开(公告)日：1998-03-24

申请号：US557904

申请日：1995-11-14

申请人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

发明人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/485 ,  H01L23/522 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002

摘要： The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

摘要翻译： 在氧化物绝缘层和氮化硅蚀刻停止层中封装半导体器件的栅极堆叠允许形成用于连接到下面的扩散区域的接触填充物，而不会发生意外扩散接触到由接触填充物产生的栅极短路的风险 。 结果，栅极堆叠可以被图案化在一起，从而减小电池尺寸并增加电池密度。 此外，使用蚀刻停止层使得接触光刻更容易，因为可以增加接触开口的尺寸并且接触对准公差变得不那么严格，而不考虑增加电池尺寸或产生与栅极短路的扩散接触。