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104 条记录 (耗时 0.039 秒)

    DMA transfer controller
    32.
    发明申请
    DMA transfer controller 有权
    DMA传输控制器

    公开(公告)号：US20050050241A1

    公开(公告)日：2005-03-03

    申请号：US10901294

    申请日：2004-07-29

    申请人： Akihiro Furuta ,  Nobuo Higaki ,  Tetsuya Tanaka ,  Tsuneyuki Suzuki

    发明人： Akihiro Furuta ,  Nobuo Higaki ,  Tetsuya Tanaka ,  Tsuneyuki Suzuki

    IPC分类号： G06F13/362 ,  G06F13/28 ,  G06F13/32

    CPC分类号： G06F13/28

    摘要： The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

    摘要翻译： 本发明提供一种DMA传输控制器，包括：传输参数存储单元，用于存储总线占用时间值，并为多个逻辑处理器中的每一个传送一组或多组DMA传输的参数; 数据传送执行单元，用于基于DMA传输参数执行DMA传输; 控制单元，用于控制DMA传输参数的接收和发送以及DMA传输的开始和中断; 以及时间测量单元，用于当为每个逻辑处理器启动第一个DMA传输时开始测量总线占用时间。 当总线占用时间达到总线占用时间值时，控制单元基于与规定序列的逻辑处理器相关的传输参数中断当前执行的DMA传输以开始DMA传输。

    Instruction converting apparatus using parallel execution code
    33.
    发明授权
    Instruction converting apparatus using parallel execution code 有权
    指令转换装置采用并行执行码

    公开(公告)号：US06324639B1

    公开(公告)日：2001-11-27

    申请号：US09280777

    申请日：1999-03-29

    申请人： Taketo Heishi ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Shuishi Takayama ,  Kensuke Odani

    发明人： Taketo Heishi ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Shuishi Takayama ,  Kensuke Odani

    IPC分类号： G06F938

    CPC分类号： G06F9/30149 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885

    摘要： A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1th unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.

    摘要翻译： 处理器可以解码具有等于一个单位字段的字长度和长度等于两个单位字段的长指令的短指令。 每种指令的操作码被布置到分配给指令的第一单位字段中。 由处理器并行执行的指令数是s。 当短指令与长指令的比率为s-1：1时，将s-1短指令分配给并行执行代码中的第s个单位字段的第一个单位字段，并将长指令分配给sth 单位字段到同一个并行执行代码中的（s + k-1）个单位字段。

    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    34.
    发明授权
    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 有权
    处理器使用较少的硬件和指令转换设备减少指令类型的数量

    公开(公告)号：US06230258B1

    公开(公告)日：2001-05-08

    申请号：US09144298

    申请日：1998-08-31

    申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    IPC分类号： G06F930

    CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

    摘要： An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition. While the judgment unit decision is negative, the conversion unit converts the conversion target instruction sequence into an instruction sequence including a conditional instruction with a condition that is mutually exclusive with the predetemiined condition.

    摘要翻译： 一种用于将不包括条件指令的指令序列转换成包括条件指令的指令序列的指令转换装置和方法，其中条件指令包括当条件满足时由处理器执行的条件和操作代码两者。 获取单元接收不包括条件指令的指令序列，由此当满足预定条件时，指令序列检测单元检测到将不同转移对象传送到同一存储资源的转换目标指令序列。 判断单元判断专用处理器的指令集是否被分配条件指令，该条件指令包括与前提条件相同的条件，由此转换单元然后可以将转换目标指令序列转换为包括具有预定条件的条件指令的指令序列。 当判断单元判定为否定时，转换单元将转换目标指令序列转换成具有条件的条件指令的指令序列，该条件与预先设定的条件相互排斥。

    Data processing having a variable number of pipeline stages
    36.
    发明授权
    Data processing having a variable number of pipeline stages 失效
    数据处理具有可变数量的流水线级

    公开(公告)号：US6018796A

    公开(公告)日：2000-01-25

    申请号：US825479

    申请日：1997-03-28

    申请人： Masato Suzuki ,  Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

    发明人： Masato Suzuki ,  Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

    IPC分类号： G06F9/38 ,  G06F15/00

    CPC分类号： G06F9/3867

    摘要： A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

    摘要翻译： 数据处理器包括一个处理单元，处理流水线阶段的指令，其数量可在n和m之间切换，m是比n大的数字。 数据处理器还包括用于在n和m之间切换处理单元的流水线级数的切换单元。 切换单元包括指示单元，用于指示数据处理器是处于第一操作状态还是处于第二操作状态，这取决于为数据处理器提供的操作时钟的频率或提供给数据处理器的电源电压 处理器和流水线控制单元，用于在第一操作条件下命令处理单元在n个阶段中操作，并且用于在第二操作条件下命令处理单元以m级操作。

    Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing
    37.
    发明授权
    Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing 失效
    可以有利地执行由正转换和饱和计算处理组成的舍入处理的处理器

    公开(公告)号：US5974540A

    公开(公告)日：1999-10-26

    申请号：US980676

    申请日：1997-12-01

    申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

    发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

    IPC分类号： G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F7/38

    CPC分类号： G06F9/3001 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/49921

    摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

    摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000-00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24输出由常数发生器21产生的最大值“0x0000-00FF”，由零发生器25产生的零值“0x0000-0000”和和积结果寄存器6的保持值之一 数据总线18。

    Compiler and processor for processing loops at high speed
    38.
    发明授权
    Compiler and processor for processing loops at high speed 失效
    用于高速处理回路的编译器和处理器

    公开(公告)号：US5850551A

    公开(公告)日：1998-12-15

    申请号：US588051

    申请日：1996-01-22

    申请人： Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

    发明人： Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/45

    CPC分类号： G06F9/3804 ,  G06F8/447 ,  G06F9/325

    摘要： A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop. A processor comprises: a pipeline comprising: an instruction fetching unit, an instruction decoding unit, and an executing unit; a branch target storage unit; a branch target registering unit for, after the instruction decoding unit has decoded a first loop exclusive instruction, registering branch target information of an instruction succeeding to the first loop exclusive instruction in the branch target registering unit; and a branch executing unit for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage unit, and controlling the pipeline so that the program executes the loop using the read branch target information.

    摘要翻译： 编译器包括一个用于提取循环信息的循环检测单元和一个生成第一循环专用指令的高速循环应用单元，在循环进入之前立即进行指令，产生第二循环专用指令，并将指令置于 每个地方分支到循环的入口。 一种处理器，包括：流水线，包括：指令获取单元，指令解码单元和执行单元; 分支目标存储单元; 分支目标登记单元，用于在所述指令解码单元解码了第一循环专用指令之后，将在所述分支目标登记单元中的所述第一循环专用指令之后的指令的分支目标信息注册; 以及分支执行单元，用于在解码单元解码了第二循环专用指令之后，判断是否执行循环，如果判断执行，读取登记在分支目标存储单元中的分支目标信息，并且控制流水线，使得 该程序使用读分支目标信息执行循环。

    Interrupt control device for processing interrupt request signals that are greater than interrupt level signals
    39.
    发明授权
    Interrupt control device for processing interrupt request signals that are greater than interrupt level signals 失效
    用于处理大于中断电平信号的中断请求信号的中断控制装置

    公开(公告)号：US5748970A

    公开(公告)日：1998-05-05

    申请号：US640082

    申请日：1996-04-30

    申请人： Shinya Miyaji ,  Nobuo Higaki

    发明人： Shinya Miyaji ,  Nobuo Higaki

    IPC分类号： G06F9/48 ,  G06F13/24 ,  G06F9/46

    CPC分类号： G06F13/24

    摘要： An interrupt control device of an embedded microcomputer including I/O devices and a processor core comprising: a program storage unit for storing interrupt processing programs, each corresponding to an interrupt level of an interrupt request signal, in sequential areas; a start address hold unit for holding start addresses, which can be updated, of the interrupt processing programs; a level hold unit for holding an interrupt level, which can be updated, of each interrupt signal inputted from the I/O devices; an interrupt reception unit for, when at least one of the interrupt signals is inputted, receiving an interrupt signal of a highest interrupt level out of the inputted interrupt signals and outputting an interrupt request signal of the same interrupt level; and a control unit for controlling a branch, when the interrupt request signal is outputted, by fetching one of the start addresses which corresponds to the interrupt level of the interrupt request signal from the start address hold unit and setting the start address in the program counter.

    摘要翻译： 一种包括I / O设备和处理器核心的嵌入式微型计算机的中断控制装置，包括：程序存储单元，用于在顺序区域中存储每个对应于中断请求信号的中断级别的中断处理程序; 开始地址保持单元，用于保持中断处理程序的可更新的起始地址; 电平保持单元，用于保持从I / O设备输入的每个中断信号的可更新的中断电平; 中断接收单元，当输入至少一个中断信号时，从所输入的中断信号中接收到最高中断电平的中断信号，并输出相同中断电平的中断请求信号; 以及控制单元，用于当输出中断请求信号时，通过从起始地址保持单元中取出与中断请求信号的中断电平相对应的起始地址中的一个并在程序计数器中设置起始地址来控制分支 。