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    Feed-forward technique for power supply rejection ratio improvement of bit line
    31.
    发明授权
    Feed-forward technique for power supply rejection ratio improvement of bit line 有权
    前馈技术的电源抑制比提高了位线

    公开(公告)号：US09148596B1

    公开(公告)日：2015-09-29

    申请号：US14247855

    申请日：2014-04-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Tianjia Sun ,  Rui Wang ,  Liping Deng ,  Tiejun Dai

    IPC: H04N5/369 ,  H04N5/357

    CPC classification number: H04N5/3698 ,  H04N5/357 ,  H04N5/378

    Abstract: An image sensor read out circuit includes a first current mirror circuit in which a second current conducted through a second current path is controlled in response to a first current conducted through the first current path. The second current is conducted through an amplifier transistor of a pixel circuit. A first current source is coupled to the first current path to provide a substantially constant current component of the first current. A second current source is coupled to a power supply rail of the pixel circuit and coupled to the first current path to provide a ripple current component of the first current. The ripple current component provided by the second current source is responsive to a ripple in the power supply rail. The first current is responsive to a sum of the currents from the first and second current sources.

    Abstract translation: 图像传感器读出电路包括第一电流镜电路，其中响应于通过第一电流路径传导的第一电流来控制通过第二电流路径传导的第二电流。 第二电流通过像素电路的放大器晶体管导通。 第一电流源耦合到第一电流路径以提供第一电流的基本上恒定的电流分量。 第二电流源耦合到像素电路的电源轨，并耦合到第一电流路径以提供第一电流的纹波电流分量。 由第二电流源提供的纹波电流分量响应于电源轨道中的纹波。 第一电流响应于来自第一和第二电流源的电流的总和。

    Acquiring global shutter-type video images with CMOS pixel array by strobing light during vertical blanking period in otherwise dark environment
    33.
    发明授权
    Acquiring global shutter-type video images with CMOS pixel array by strobing light during vertical blanking period in otherwise dark environment 有权
    在黑暗的环境下，在垂直消隐期间通过选通光线，获取具有CMOS像素阵列的全局快门式视频图像

    公开(公告)号：US09119544B2

    公开(公告)日：2015-09-01

    申请号：US13622976

    申请日：2012-09-19

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Tiejun Dai ,  Junzhao Lei

    IPC: H04N7/18 ,  H04N5/33 ,  A61B1/045 ,  H04N5/235 ,  A61B1/00 ,  A61B1/05 ,  H04N5/353 ,  H04N5/225

    CPC classification number: A61B1/045 ,  A61B1/00004 ,  A61B1/051 ,  H04N5/2256 ,  H04N5/235 ,  H04N5/2354 ,  H04N5/3532 ,  H04N2005/2255

    Abstract: A CMOS pixel array is introduced into a dark environment to acquire video image frames. During a first frame, each row of pixels is sequentially reset, one row at a time, and then each row of pixels is sequentially read out, one row at a time. During a second frame, each row of pixels is sequentially reset, one row at a time, and then each row of pixels sequentially read out, one row at a time. A light source illuminates the dark environment during a vertical blanking period between the reading of the last row during the first frame and the reading of the first row during the second frame. The light source does not illuminate the dark environment between reading the first and last rows during the first frame nor between reading the first and last rows during the second frame.

    Abstract translation: 将CMOS像素阵列引入黑暗环境中以获取视频图像帧。 在第一帧期间，每行像素被顺序复位，一次一行，然后每行像素被顺序地读出，一次一行。 在第二帧期间，每行像素被顺序复位，一次一行，然后每行像素顺序读出，一次一行。 在第一帧期间最后一行的读取和第二帧期间的第一行的读取之间的垂直消隐期间，光源照亮黑暗环境。 光源在第一帧期间在读取第一行和最后一行之间以及在第二帧期间读取第一行和最后一行之间不会照亮暗环境。

    STACKED CHIP IMAGE SENSOR WITH LIGHT-SENSITIVE CIRCUIT ELEMENTS ON THE BOTTOM CHIP
    34.
    发明申请
    STACKED CHIP IMAGE SENSOR WITH LIGHT-SENSITIVE CIRCUIT ELEMENTS ON THE BOTTOM CHIP 有权
    底部芯片上带有敏感电路元件的堆叠芯片图像传感器

    公开(公告)号：US20140103411A1

    公开(公告)日：2014-04-17

    申请号：US14033293

    申请日：2013-09-20

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Tiejun Dai ,  Guannho George Tsau

    IPC: H01L27/146

    CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464

    Abstract: An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.

    Abstract translation: 示例性成像传感器系统包括形成在第一晶片的第一半导体层中的背面照明CMOS成像阵列。 CMOS成像阵列包括N个像素，其中每个像素包括光电二极管区域。 第一晶片在第一晶片的第一金属堆叠和第二晶片的第二金属堆叠之间的结合界面处结合到第二晶片。 存储装置设置在第二晶片的第二半导体层中。 存储装置包括至少N个存储单元，其中N个存储单元中的每一个被配置为存储表示由相应光电二极管区域累积的图像电荷的信号。 每个存储单元包括对光诱导的泄漏敏感的电路元件。

    Low power single photon avalanche diode photon counter with peak current suppression technique
    35.
    发明授权
    Low power single photon avalanche diode photon counter with peak current suppression technique 有权

    公开(公告)号：US12247873B1

    公开(公告)日：2025-03-11

    申请号：US18438791

    申请日：2024-02-12

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Rui Wang ,  Tiejun Dai ,  Lindsay Alexander Grant ,  Keiji Mabuchi

    IPC: G01J1/44

    Abstract: A method of counting photons using a plurality of single photon avalanche diodes (SPADs), including initiating a detection phase, enabling each single photon avalanche diode (SPAD) of the plurality of SPADs for a period of time within the detection phase, accumulating a SPAD event from each SPAD of the plurality of SPADs, wherein each SPAD event corresponds to a detection of a single photon, determining a counter code at an end of the detection phase, where the counter code corresponds to accumulated SPAD events, and enabling one or more SPADs of the plurality of SPADs within an exposure phase based on the counter code, where the counter code is greater than an expected number of the SPAD events during the exposure phase, and where the expected number of SPAD events during the exposure phase is based on the counter code that is determined at the end of the detection phase.

    SAMPLE AND HOLD SWITCH DRIVER CIRCUITRY WITH SLOPE CONTROL
    36.
    发明申请
    SAMPLE AND HOLD SWITCH DRIVER CIRCUITRY WITH SLOPE CONTROL 有权

    公开(公告)号：US20220078360A1

    公开(公告)日：2022-03-10

    申请号：US17530316

    申请日：2021-11-18

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Zhe Gao ,  Ling Fu ,  Yu-Shen Yang ,  Tiejun Dai

    IPC: H04N5/345 ,  H04N5/369 ,  H04N5/378 ,  G11C27/02

    Abstract: A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

    Hybrid CMOS image sensor with event driven sensing
    37.
    发明授权
    Hybrid CMOS image sensor with event driven sensing 有权

    公开(公告)号：US11240454B2

    公开(公告)日：2022-02-01

    申请号：US16862337

    申请日：2020-04-29

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Zhe Gao ,  Tiejun Dai

    IPC: H04N5/3745 ,  H04N5/378

    Abstract: An image sensor includes a source follower coupled to a photodiode to generate an image signal responsive to photogenerated charge. The image signal is received by image readout circuitry through a row select transistor. A reset transistor resets the photogenerated charge. A first node of mode select circuit is coupled to the reset transistor, a second node is coupled to a pixel supply voltage, and a third node is coupled to an event driven circuit. The mode select circuit couples the first node to the second node during an imaging mode to supply the pixel supply voltage to the reset transistor. The mode select circuit is further configured to couple the first node to the third node during an event driven mode to couple a photocurrent of the photodiode to drive the event driven circuit through the reset transistor to detect changes in the photocurrent.

    Sample and hold switch driver circuitry with slope control
    38.
    发明授权
    Sample and hold switch driver circuitry with slope control 有权

    公开(公告)号：US11212467B2

    公开(公告)日：2021-12-28

    申请号：US16516067

    申请日：2019-07-18

    Applicant: OmniVision Technologies, Inc.

    Inventor： Zhe Gao ,  Ling Fu ,  Yu-Shen Yang ,  Tiejun Dai

    IPC: H04N5/345 ,  H04N5/369 ,  H04N5/378 ,  G11C27/02

    Abstract: A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.

    LAYOUT DESIGN OF DUAL ROW SELECT STRUCTURE
    39.
    发明申请
    LAYOUT DESIGN OF DUAL ROW SELECT STRUCTURE 有权

    公开(公告)号：US20210358994A1

    公开(公告)日：2021-11-18

    申请号：US17066277

    申请日：2020-10-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Sang Joo Lee ,  Rui Wang ,  Hiroaki Ebihara ,  Tiejun Dai ,  Hiroki Ui

    IPC: H01L27/146 ,  H01L27/148 ,  H04N5/378

    Abstract: A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

    High dynamic range high speed CMOS image sensor design
    40.
    发明授权
    High dynamic range high speed CMOS image sensor design 有权

    公开(公告)号：US11140352B1

    公开(公告)日：2021-10-05

    申请号：US17121423

    申请日：2020-12-14

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Tiejun Dai ,  Zhe Gao ,  Ling Fu

    IPC: H04N5/378 ,  H04N5/3745 ,  H03M1/34 ,  H04N5/355

    Abstract: A readout circuit for use in an image sensor includes a first sample and hold (SH) circuit coupled to a bitline that is coupled to a pixel array. A second SH circuit is coupled to the bitline. A bypass switch is coupled to the bitline, the first SH circuit, and the second SH circuit. An analog to digital converter (ADC) is coupled to the bypass switch. The bypass switch is configured to provide an image charge value from the pixel array to the ADC through the bitline, or through one of the first SH circuit or the second SH circuit in response to a switch select signal.

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