公开(公告)号：US20110078641A1

公开(公告)日：2011-03-31

申请号：US12569421

申请日：2009-09-29

Applicant: James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

Inventor： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

Abstract translation: 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US20100269079A1

公开(公告)日：2010-10-21

申请号：US12426475

申请日：2009-04-20

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07805693B2

公开(公告)日：2010-09-28

申请号：US12031734

申请日：2008-02-15

Applicant: Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Abstract translation: 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。

公开(公告)号：US20090278222A1

公开(公告)日：2009-11-12

申请号：US12117771

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC: H01L27/00 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072

Abstract: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

Abstract translation: 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

公开(公告)号：US20090222783A1

公开(公告)日：2009-09-03

申请号：US12039109

申请日：2008-02-28

Applicant: James A. Culp ,  Gregory A. Northrop ,  Ming Yin

Inventor： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract translation: 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部电池或内部视图包括形成电池组件的规则形状，并定义电池构造细节，并通过构造进行接地规则清洁，或通过仿真或硬件验证。

公开(公告)号：US07473648B2

公开(公告)日：2009-01-06

申请号：US11308106

申请日：2006-03-07

Applicant: Timothy A. Brunner ,  James A. Culp ,  Lars W. Liebmann

Inventor： Timothy A. Brunner ,  James A. Culp ,  Lars W. Liebmann

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76895 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/28123

Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

Abstract translation: 形成平面CMOS晶体管的方法将形成栅极层的步骤分成用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后用栅极焊盘和局部互连的图案蚀刻多晶硅，从而减少来自不同曝光区域的衍射数量和其它串扰。

公开(公告)号：US20080279443A1

公开(公告)日：2008-11-13

申请号：US12182409

申请日：2008-07-30

Applicant: Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

Inventor： Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

IPC: G06K9/74

CPC classification number: G03F7/70441

Abstract: A mask inspection method and system. Provided is a mask fabrication database describing geometrical shapes S to be printed as part of a mask pattern on a reticle to fabricate a mask through use of a mask fabrication tooling. The shapes S appear on the mask as shapes S′ upon being printed. At least one of the shapes S′ may be geometrically distorted relative to a corresponding at least one of the shapes S due to a lack of precision in the mask fabrication tooling. Also provided is a mask inspection database to be used for inspecting the mask after the mask has been fabricated by the mask fabrication tooling. The mask inspection database describes shapes S″ approximating the shapes S′. A geometric distortion between the shapes S′ and S″ is less than a corresponding geometric distortion between the shapes S′ and S.

Abstract translation: 面罩检查方法和系统。 提供了一种掩模制造数据库，其描述要在掩模版上作为掩模图案的一部分打印的几何形状S，以通过使用掩模制造工具来制造掩模。 形状S在印刷时作为形状S'出现在掩模上。 由于在掩模制造工具中缺乏精度，至少一种形状S'可能相对于形状S中的相应的至少一个形状几何失真。 还提供了掩模检查数据库，用于在通过掩模制造工具制造掩模之后检查掩模。 掩模检查数据库描述形状S'近似形状S'。 形状S'和S“之间的几何变形小于形状S'和S之间的对应的几何变形。

公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US08302068B2

公开(公告)日：2012-10-30

申请号：US12689481

申请日：2010-01-19

Applicant: James A. Culp ,  Lars W. Liebmann

Inventor： James A. Culp ,  Lars W. Liebmann

IPC: G06F15/04 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract translation: 本发明提供了一种用于设计用于由基于模型的设计工具（例如OPC或OPC验证）使用的晶圆上目标的方法和计算机程序产品。 通过修改关键尺寸来修改晶圆上目标，以改善或优化电特性，同时还确保满足一个或多个屈服约束。 使用电气优化的目标可以产生更符合设计者意图的经济高效的面罩设计。

公开(公告)号：US08232215B2

公开(公告)日：2012-07-31

申请号：US12622557

申请日：2009-11-20

Applicant: James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L21/302

CPC classification number: H01L21/31144

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract translation: 用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。 保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。 用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻 的部分蚀刻的间隔材料层。 用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。