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    LEAKAGE AWARE DESIGN POST-PROCESSING
    2.
    发明申请
    LEAKAGE AWARE DESIGN POST-PROCESSING 有权
    漏洞设计后处理

    公开(公告)号：US20110179391A1

    公开(公告)日：2011-07-21

    申请号：US12689481

    申请日：2010-01-19

    Applicant: James A. Culp ,  Lars W. Liebmann

    Inventor： James A. Culp ,  Lars W. Liebmann

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

    Abstract translation: 本发明提供了一种用于设计用于由基于模型的设计工具（例如OPC或OPC验证）使用的晶圆上目标的方法和计算机程序产品。 通过修改关键尺寸来修改晶圆上目标，以改善或优化电特性，同时还确保满足一个或多个屈服约束。 使用电气优化的目标可以产生更符合设计者意图的经济高效的面罩设计。

    Automated sensitivity definition and calibration for design for manufacturing tools
    3.
    发明授权
    Automated sensitivity definition and calibration for design for manufacturing tools 有权
    自动灵敏度定义和校准用于制造工具的设计

    公开(公告)号：US08141027B2

    公开(公告)日：2012-03-20

    申请号：US12652409

    申请日：2010-01-05

    Applicant: James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

    Inventor： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

    Abstract translation: 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

    Double exposure double resist layer process for forming gate patterns
    4.
    发明授权
    Double exposure double resist layer process for forming gate patterns 失效
    用于形成栅极图案的双曝光双光刻胶层工艺

    公开(公告)号：US07473648B2

    公开(公告)日：2009-01-06

    申请号：US11308106

    申请日：2006-03-07

    Applicant: Timothy A. Brunner ,  James A. Culp ,  Lars W. Liebmann

    Inventor： Timothy A. Brunner ,  James A. Culp ,  Lars W. Liebmann

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/76895 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/28123

    Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

    Abstract translation: 形成平面CMOS晶体管的方法将形成栅极层的步骤分成用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后用栅极焊盘和局部互连的图案蚀刻多晶硅，从而减少来自不同曝光区域的衍射数量和其它串扰。

    Leakage aware design post-processing
    5.
    发明授权
    Leakage aware design post-processing 有权
    泄漏感知设计后处理

    公开(公告)号：US08302068B2

    公开(公告)日：2012-10-30

    申请号：US12689481

    申请日：2010-01-19

    Applicant: James A. Culp ,  Lars W. Liebmann

    Inventor： James A. Culp ,  Lars W. Liebmann

    IPC: G06F15/04 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

    Abstract translation: 本发明提供了一种用于设计用于由基于模型的设计工具（例如OPC或OPC验证）使用的晶圆上目标的方法和计算机程序产品。 通过修改关键尺寸来修改晶圆上目标，以改善或优化电特性，同时还确保满足一个或多个屈服约束。 使用电气优化的目标可以产生更符合设计者意图的经济高效的面罩设计。

    Electrically driven optical proximity correction
    7.
    发明授权
    Electrically driven optical proximity correction 有权
    电驱动光学邻近校正

    公开(公告)号：US07865864B2

    公开(公告)日：2011-01-04

    申请号：US12024188

    申请日：2008-02-01

    Applicant: Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

    Inventor： Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

    Abstract translation: 描述了提供电驱动光学邻近校正的方法。 在一个实施例中，存在执行电驱动光学邻近校正的方法。 在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。 在掩模布局上运行光刻仿真。 从掩模布局的每层的光刻模拟的输出中提取电特性。 确定提取的电特性是否与目标电特性一致。 响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

    OPC trimming for performance
    8.
    发明授权
    OPC trimming for performance 失效
    OPC修剪性能

    公开(公告)号：US07627836B2

    公开(公告)日：2009-12-01

    申请号：US11164044

    申请日：2005-11-08

    Applicant: James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

    Inventor： James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

    Abstract translation: 基于使用光学邻近校正技术的方法，在芯片制造之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

    ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION
    9.
    发明申请
    ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION 有权
    电动驱动光学临近校正

    公开(公告)号：US20090199151A1

    公开(公告)日：2009-08-06

    申请号：US12024188

    申请日：2008-02-01

    Applicant: Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

    Inventor： Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

    Abstract translation: 描述了提供电驱动光学邻近校正的方法。 在一个实施例中，存在执行电驱动光学邻近校正的方法。 在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。 在掩模布局上运行光刻仿真。 从掩模布局的每层的光刻模拟的输出中提取电特性。 确定提取的电特性是否与目标电特性一致。 响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

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