公开(公告)号：US07718480B1

公开(公告)日：2010-05-18

申请号：US11138221

申请日：2005-05-26

申请人： Vladislav Vashchenko ,  Marcel ter Book ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Marcel ter Book ,  Peter J. Hopper

IPC分类号： H01L21/00

CPC分类号： H01L27/0266 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/78

摘要： In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.

摘要翻译： 在具有多个源极和漏极触点的NMOS有源钳位装置和NMOS有源钳位阵列中，通过包括至少部分地形成在源极中的一个或多个p +区域并且电连接到 一个或多个源接触。

公开(公告)号：US07639464B1

公开(公告)日：2009-12-29

申请号：US11376492

申请日：2006-03-15

申请人： Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H02H9/00 ,  H02H3/20

CPC分类号： H01L27/0266

摘要： In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.

摘要翻译： 在双向ESD保护结构中，第一和第二NMOS器件通过使用公共浮动互连连接它们的漏极或其源极而被背对背地串联连接，同时确保器件保持彼此隔离。

公开(公告)号：US07635614B1

公开(公告)日：2009-12-22

申请号：US11724622

申请日：2007-03-15

申请人： Vladimir Kuznetsov ,  Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladimir Kuznetsov ,  Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H01L21/323 ,  H01L29/74

CPC分类号： H01L29/7436 ,  H01L29/7404 ,  H01L29/749

摘要： An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.

摘要翻译： 基于LDMOS制造工艺的NLDMOS SCR器件包括提供可控开关特性以允许其用于快速开关电压调节器的ESD保护的双栅极。

公开(公告)号：US20090162978A1

公开(公告)日：2009-06-25

申请号：US12395506

申请日：2009-02-27

申请人： Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H01L21/332

CPC分类号： H01L27/0259

摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

摘要翻译： 用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。 通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

公开(公告)号：US07479435B1

公开(公告)日：2009-01-20

申请号：US11007565

申请日：2004-12-08

申请人： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

发明人： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

IPC分类号： H01L29/788

CPC分类号： H01L21/26586 ,  H01L21/2652 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847

摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.

摘要翻译： 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。

公开(公告)号：US07394133B1

公开(公告)日：2008-07-01

申请号：US11216774

申请日：2005-08-31

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

IPC分类号： H01L29/72

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/87

摘要： In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.

摘要翻译： 在ESD保护结构中，通过在NMOS器件周围形成n阱隔离环来提供双向ESD保护，使得形成NMOS漏极的p阱通过n阱与下面的p衬底隔离 隔离环。 通过形成n阱隔离环，提供了用于反向ESD保护的嵌入式SCR的p-n-p-n结构。 调整n阱隔离环的宽度及其与NMOS漏极的间隔，以提供所需的SCR参数。

公开(公告)号：US07218555B2

公开(公告)日：2007-05-15

申请号：US11242094

申请日：2005-10-03

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/14603 ,  H01L27/14609

摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

摘要翻译： 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

公开(公告)号：US07209503B1

公开(公告)日：2007-04-24

申请号：US10838671

申请日：2004-05-03

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC分类号： H01S5/00

CPC分类号： H01L27/1446 ,  H01L27/146

摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.

摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。

公开(公告)号：US07113427B1

公开(公告)日：2006-09-26

申请号：US11076711

申请日：2005-03-09

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7881

摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。

公开(公告)号：US07075341B1

公开(公告)日：2006-07-11

申请号：US10823455

申请日：2004-04-13

申请人： Vladislav Vashchenko ,  Yuri Mirgorodski ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Yuri Mirgorodski ,  Peter J. Hopper

IPC分类号： H03B1/00

CPC分类号： H01L27/0266

摘要： A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.

摘要翻译： 提供消耗片上低空间的线性时间驱动电路。 时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。