公开(公告)号：US20110115071A1

公开(公告)日：2011-05-19

申请号：US13013563

申请日：2011-01-25

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane ,  Reda R. Razouk

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane ,  Reda R. Razouk

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

摘要翻译： 描述了用于形成集成电路封装的各种装置和方法。 本发明的一个方面涉及一种集成电路封装，其中一个或多个集成电路嵌入在基片中并被一层可光成像的环氧树脂覆盖。 基板可以由各种材料制成，包括硅，石英和玻璃。 集成电路位于衬底的顶表面中的空腔内。 环氧树脂层形成在衬底的顶表面和集成电路的有源面上。 在环氧树脂层上形成互连层并与集成电路电耦合。

公开(公告)号：US20110095365A1

公开(公告)日：2011-04-28

申请号：US12589491

申请日：2009-10-23

申请人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

发明人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L29/7835 ,  H01L21/76898 ,  H01L29/407 ,  H01L29/66659

摘要： A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.

摘要翻译： 一种方法包括在绝缘体上半导体结构的第一侧上形成晶体管器件。 绝缘体上半导体结构包括衬底，电介质层和衬底和电介质层之间的掩埋层。 该方法还包括通过绝缘体上半导体结构形成导电插塞。 导电插头与晶体管器件电连接。 该方法还包括在绝缘体上半导体结构的第二侧上形成场板，其中场板与导电插头电连接。 晶体管器件可以具有至少600V的击穿电压，并且场板可以沿着晶体管器件的长度的至少40％延伸。

公开(公告)号：US07842544B2

公开(公告)日：2010-11-30

申请号：US12479713

申请日：2009-06-05

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/50 ,  H01L21/48

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/552 ,  H01L23/642 ,  H01L23/645 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/112 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias.

摘要翻译： 描述了用于形成集成电路封装的各种装置和方法。 本发明的一个方面涉及用于封装微系统的晶片级方法。 可以提供用金属通孔预制的基板。 衬底也可以通过在衬底中形成孔并且将导电材料电镀到孔中以形成通孔来制造。 多个微系统形成在衬底的顶表面上。 每个微系统被形成为包括多层平坦化，光可光刻环氧树脂，一个或多个互连层和集成电路。 每个互连层嵌入相关联的环氧树脂层。 集成电路位于至少相关的环氧树脂层内。 微系统的互连层形成为使得至少一些互连层与衬底中的一个或多个金属通孔电耦合。 将成型材料施加在基板的顶表面和微系统上以形成模制结构。 可以去除基底的一部分。 模制结构可以被单个化以形成单独的集成电路封装。 每个集成电路封装包含至少一个微系统。 各种实施例涉及在衬底的顶表面上形成导电焊盘，而不是金属过孔。

公开(公告)号：US07755463B2

公开(公告)日：2010-07-13

申请号：US12250382

申请日：2008-10-13

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01F21/06 ,  H01F27/30 ,  H01F27/24 ,  H02M1/00 ,  G05F1/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

摘要： The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes.

摘要翻译： 所要求保护的发明涉及电感器和集成电路芯片的布置。 一个实施例涉及其上形成有电感器的集成电路管芯。 电感器包括具有绕组输入和绕组输出的电感器绕组。 电感器还包括电感器芯阵列，其具有与电感器绕组磁耦合的至少第一组和第二组电感器芯体元件。 第一组电感器芯元件中的每个电感器芯体元件由第一金属材料形成。 第二组电感器芯元件中的每个电感器芯体元件由具有与第一磁性材料不同的磁矫顽力的第二金属材料形成。 电感器还包括一组将电感器芯元件电隔离的间隔件。 一些实施例涉及以各种方式磁性相互作用的多个电感器绕组和/或多个电感器核心元件。 具体实施方案涉及具有不同组成和/或尺寸的核心元件。

公开(公告)号：US20090181473A1

公开(公告)日：2009-07-16

申请号：US12275599

申请日：2008-11-21

申请人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

发明人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

IPC分类号： H01L21/02 ,  H01F7/127

CPC分类号： H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49144 ,  H01L2924/00

摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.

摘要翻译： 利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。 磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。 硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。 因此，由电感线圈产生的磁场与硬磁轴平行和自对准。 通过在平行于容易轴的施加磁场中电镀来增强易轴。

公开(公告)号：US20090094818A1

公开(公告)日：2009-04-16

申请号：US11973861

申请日：2007-10-10

申请人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

发明人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

IPC分类号： H01F41/04

CPC分类号： H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49144 ,  H01L2924/00

摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.

摘要翻译： 利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。 磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。 硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。 因此，由电感线圈产生的磁场与硬磁轴平行和自对准。 可以通过在平行于容易轴的施加磁场中电镀来增强易轴。

公开(公告)号：US20090040000A1

公开(公告)日：2009-02-12

申请号：US12250382

申请日：2008-10-13

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

摘要： The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes.

摘要翻译： 所要求保护的发明涉及电感器和集成电路芯片的布置。 一个实施例涉及其上形成有电感器的集成电路管芯。 电感器包括具有绕组输入和绕组输出的电感器绕组。 电感器还包括电感器芯阵列，其具有与电感器绕组磁耦合的至少第一组和第二组电感器芯体元件。 第一组电感器芯元件中的每个电感器芯体元件由第一金属材料形成。 第二组电感器芯元件中的每个电感器芯体元件由具有与第一磁性材料不同的磁矫顽力的第二金属材料形成。 电感器还包括一组将电感器芯元件电隔离的间隔件。 一些实施例涉及以各种方式磁性相互作用的多个电感器绕组和/或多个电感器核心元件。 具体实施方案涉及具有不同组成和/或尺寸的核心元件。

公开(公告)号：US07468899B1

公开(公告)日：2008-12-23

申请号：US11621424

申请日：2007-01-09

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

IPC分类号： G05F1/59 ,  G05F1/618

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive a plurality of pulsed input signals having a predetermined duty cycle and a plurality of inductor windings associated with each of the plurality of regulator circuits respectively. The integrated circuit also includes a core array having a plurality of core elements. The plurality of core elements are positioned adjacent to and magnetically coupled with one or more of the plurality of inductor windings. An output node is electrically coupled to the plurality of inductor windings. The output signal at the output node is the sum of the instantaneous voltage on each of the inductor windings associated with the plurality of regulator circuits respectively. The integrated circuit also includes a phase control circuit coupled to the plurality of regulator circuits. The phase control circuit controls the phase of the plurality of pulsed input signals received at the plurality of the regulator circuits to control the output signal at the output node.

摘要翻译： 公开了一种直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。 集成电路包括多个调节器电路，每个调节器电路具有被配置为分别接收具有预定占空比的多个脉冲输入信号和与多个调节器电路中的每一个相关联的多个电感器绕组的输入节点。 集成电路还包括具有多个核心元件的芯阵列。 多个芯元件被定位成与多个电感器绕组中的一个或多个相邻并且磁耦合。 输出节点电耦合到多个电感器绕组。 输出节点处的输出信号分别是与多个调节器电路相关联的每个电感器绕组上的瞬时电压之和。 集成电路还包括耦合到多个调节器电路的相位控制电路。 相位控制电路控制在多个调节器电路处接收的多个脉冲输入信号的相位，以控制输出节点处的输出信号。

公开(公告)号：US08130067B2

公开(公告)日：2012-03-06

申请号：US12777654

申请日：2010-05-11

申请人： Dok Won Lee ,  Peter Smeys ,  Anuraag Mohan ,  Peter J. Hopper

发明人： Dok Won Lee ,  Peter Smeys ,  Anuraag Mohan ,  Peter J. Hopper

IPC分类号： H01F5/00 ,  G01R33/02 ,  C21D1/04

CPC分类号： H01F19/04 ,  H01F5/003 ,  H01F17/08 ,  H01F27/2895 ,  H01F41/046 ,  H01L23/645 ,  H01L2924/0002 ,  Y10T29/49071 ,  H01L2924/00

摘要： A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the primary windings. The core can also be formed to have a number of sections where the magnetic flux follows the hard axis through each section of the core.

摘要翻译： 半导体变压器通过将变压器的初级绕组围绕磁性材料的一部分形成高频操作，所述磁性材料的一部分具有基本上平行于由初级绕组产生的磁场的方向的硬轴。 芯也可以形成为具有多个部分，其中磁通量通过芯的每个部分跟随硬轴。

公开(公告)号：US06613615B2

公开(公告)日：2003-09-02

申请号：US09976728

申请日：2001-10-12

申请人： Jack A. Mandelman ,  Fariborz Assaderaghi ,  Michael J. Hargrove ,  Peter Smeys ,  Norman J. Rohrer

发明人： Jack A. Mandelman ,  Fariborz Assaderaghi ,  Michael J. Hargrove ,  Peter Smeys ,  Norman J. Rohrer

IPC分类号： H01L2100

CPC分类号： H01L27/10897 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  Y10S257/901 ,  Y10S257/908

摘要： A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.