公开(公告)号：US20070211510A1

公开(公告)日：2007-09-13

申请号：US11409628

申请日：2006-04-24

申请人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

发明人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

IPC分类号： G11C11/22 ,  G11C5/06 ,  G11C11/42

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

申请人： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

发明人： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22

摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US5491809A

公开(公告)日：1996-02-13

申请号：US764

申请日：1993-01-05

申请人： Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy

发明人： Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/22 ,  G11C16/34 ,  G06F12/16

CPC分类号： G11C16/3445 ,  G11C16/22 ,  G11C16/344

摘要： A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

摘要翻译： 一种用于擦除非易失性存储器的块的方法，包括：检测块是否处于擦除状态或从擦除中保护的状态中的至少一个; 然后将每个被检测到的块中的每个块设置为处于擦除状态或从擦除保护的状态中的至少一个或者对于不被检测到的每个块的第二级的标志寄存器; 然后选择其各自的标志设置在第二级的擦除块; 然后擦除所选的块。

公开(公告)号：US5218568A

公开(公告)日：1993-06-08

申请号：US809462

申请日：1991-12-17

申请人： Sung-Wei Lin ,  Manzur Gill ,  Inn K. Lee

发明人： Sung-Wei Lin ,  Manzur Gill ,  Inn K. Lee

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.

摘要翻译： 电可擦除的电可编程只读存储单元10形成在第一导电类型的半导体层30的表面。 第一源极/漏极区域16和第二源极/漏极区域20形成在与第一导电类型相反并且由第一沟道区域50间隔开的第二导电类型的半导体层30的表面中。第三源极/漏极区域 18形成在第二导电类型的半导体层30的表面上，第二导电类型的第二导电类型与第二源极/漏极区域20间隔开第二沟道区域52.邻近第二源极/漏极区域20的至少一部分形成厚的绝缘体区域44， 包括覆盖第二源极/漏极区域20的相应横向边缘的倾斜厚度的横向边缘。第二源极/漏极区域20的对应横向边缘具有与厚度绝缘体的上覆侧边缘的倾斜厚度成正比的渐变掺杂剂浓度 差分生长的绝缘体区域54覆盖第二源极/漏极区域20并且包括倾斜厚度的侧向边缘。 薄的绝缘体隧道窗口62覆盖在第二源极/漏极区域20的区域60之间，形成在厚绝缘体区域44的侧边缘之间并且间隔着厚的绝缘体区域44的侧边缘和差分生长的绝缘体区域54的横向边缘之间的隧道窗口62.浮动栅极导体26 被布置在相邻的隧道窗口62和绝对相邻的第二通道区域52处。控制栅极导体28被隔离地邻近浮置栅极导体28设置。栅极导体24与第一沟道区域50绝缘地邻近设置。

公开(公告)号：US5155055A

公开(公告)日：1992-10-13

申请号：US685358

申请日：1991-04-15

申请人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

发明人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883

摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

摘要翻译： 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US5008721A

公开(公告)日：1991-04-16

申请号：US494042

申请日：1990-03-15

申请人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

发明人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883 ,  Y10S257/903

摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

摘要翻译： 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US07813198B2

公开(公告)日：2010-10-12

申请号：US12102125

申请日：2008-04-14

申请人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

发明人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

IPC分类号： G11C7/00

CPC分类号： G11C16/28 ,  G11C16/30

摘要： One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

摘要翻译： 本发明的一个实施例包括存储器系统。 该系统包括耦合到位线节点的存储器单元。 存储器单元可被配置为在读取操作期间响应于偏置电压而在位线节点上产生位线电流。 该系统还包括读出放大器，其被配置为在预充电阶段期间保持位线节点的基本上恒定的电压幅值，并且基于调节到位线节点和从位线节点的电流流动来读取操作的感测相位，以及 以在读取操作期间基于位线节点上的位线电流的大小来确定闪存晶体管的存储器值。

公开(公告)号：US20080079471A1

公开(公告)日：2008-04-03

申请号：US11937303

申请日：2007-11-08

申请人： Sung-Wei Lin ,  Sudhir Madan ,  John Fong

发明人： Sung-Wei Lin ,  Sudhir Madan ,  John Fong

IPC分类号： H03K5/01

CPC分类号： H03K19/00346 ,  H03K19/185

摘要： A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850 ) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

摘要翻译： 公开了一种减少字线耦合的存储电路和方法。 电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。 第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。 第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。 第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

公开(公告)号：US07301795B2

公开(公告)日：2007-11-27

申请号：US11260987

申请日：2005-10-28

申请人： John Y. Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Kumar Madan ,  Jarrod Eliason

发明人： John Y. Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Kumar Madan ,  Jarrod Eliason

IPC分类号： G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

公开(公告)号：US20070058413A1

公开(公告)日：2007-03-15

申请号：US11227936

申请日：2005-09-15

申请人： Sung-Wei Lin ,  Sudhir Madan

发明人： Sung-Wei Lin ,  Sudhir Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C7/12 ,  G11C7/14

摘要： Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line. The method may further optionally comprise grounding the dummy bit line after pulsing the plate line, and optionally disabling the word line after grounding the dummy bit line to precondition the cell for the next memory operation.

摘要翻译： 描述了用于以避免在存储器阵列的边缘处沿着虚拟位线的存储器单元中的栅极氧化物的过压击穿的方式来操作FeRAM和其它这样的存储器件的方法，所述方法包括在板期间浮置虚拟位线 线脉冲活动。 在本发明的一个实施方式中，该方法被应用于具有板线，伪位线，传输晶体管和铁电存储电容器的FeRAM虚拟单元。 该方法包括首先将虚拟位线接地作为优选的前提条件，然而，如果存储电容器的存储节点以其他方式接地，则该步骤可以被认为是可选步骤。 该方法然后包括浮置虚拟位线，激活与存储器单元相关联的字线，以及脉冲板线。 或者，该方法包括将代替虚拟位线或浮置虚拟位线之前的正电压偏压施加到虚拟位线。 该方法可以进一步可选地包括在脉冲板线之后对虚拟位线进行接地，并且可选地在使虚拟位线接地之后禁用字线，以对单元进行下一个存储器操作的预处理。