公开(公告)号：US20090034338A1

公开(公告)日：2009-02-05

申请号：US12102125

申请日：2008-04-14

申请人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

发明人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/28 ,  G11C16/30

摘要： One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

摘要翻译： 本发明的一个实施例包括存储器系统。 该系统包括耦合到位线节点的存储器单元。 存储器单元可被配置为在读取操作期间响应于偏置电压而在位线节点上产生位线电流。 该系统还包括读出放大器，其被配置为在预充电阶段期间保持位线节点的基本上恒定的电压幅值，并且基于调节到位线节点和从位线节点的电流流动来读取操作的感测相位，以及 以在读取操作期间基于位线节点上的位线电流的大小来确定闪存晶体管的存储器值。

公开(公告)号：US07813198B2

公开(公告)日：2010-10-12

申请号：US12102125

申请日：2008-04-14

申请人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

发明人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

IPC分类号： G11C7/00

CPC分类号： G11C16/28 ,  G11C16/30

摘要： One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

摘要翻译： 本发明的一个实施例包括存储器系统。 该系统包括耦合到位线节点的存储器单元。 存储器单元可被配置为在读取操作期间响应于偏置电压而在位线节点上产生位线电流。 该系统还包括读出放大器，其被配置为在预充电阶段期间保持位线节点的基本上恒定的电压幅值，并且基于调节到位线节点和从位线节点的电流流动来读取操作的感测相位，以及 以在读取操作期间基于位线节点上的位线电流的大小来确定闪存晶体管的存储器值。

公开(公告)号：US07463504B2

公开(公告)日：2008-12-09

申请号：US11227936

申请日：2005-09-15

申请人： Sung-Wei Lin ,  Sudhir Madan

发明人： Sung-Wei Lin ,  Sudhir Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C7/12 ,  G11C7/14

摘要： Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line. The method may further optionally comprise grounding the dummy bit line after pulsing the plate line, and optionally disabling the word line after grounding the dummy bit line to precondition the cell for the next memory operation.

摘要翻译： 描述了用于以避免在存储器阵列的边缘处沿着虚拟位线的存储器单元中的栅极氧化物的过压击穿的方式来操作FeRAM和其它这样的存储器件的方法，所述方法包括在板期间浮置虚拟位线 线脉冲活动。 在本发明的一个实施方式中，该方法被应用于具有板线，伪位线，传输晶体管和铁电存储电容器的FeRAM虚拟单元。 该方法包括首先将虚拟位线接地作为优选的前提条件，然而，如果存储电容器的存储节点以其他方式接地，则该步骤可以被认为是可选步骤。 该方法然后包括浮置虚拟位线，激活与存储器单元相关联的字线，以及脉冲板线。 或者，该方法包括将代替虚拟位线或浮置虚拟位线之前的正电压偏压施加到虚拟位线。 该方法可以进一步可选地包括在脉冲板线之后对虚拟位线进行接地，并且可选地在使虚拟位线接地之后禁用字线，以对单元进行下一个存储器操作的预处理。

公开(公告)号：US07443708B2

公开(公告)日：2008-10-28

申请号：US11409628

申请日：2006-04-24

申请人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  John Fong

发明人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  John Fong

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US5657268A

公开(公告)日：1997-08-12

申请号：US560670

申请日：1995-11-20

申请人： Phat C. Truong ,  Sung-Wei Lin

发明人： Phat C. Truong ,  Sung-Wei Lin

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/16 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C16/16

摘要： In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector. An erasing method includes connecting the wordlines to a reference voltage, connecting at least one deselected common array-source line to each bitline coupled to drains of columns of memory cells in the deselected sector, then biasing at a positive voltage both the deselected common array-source line and said bitlines coupled to drains of memory cells in columns of the deselected sector, and then applying a positive erasing voltage to said common array-source line of the selected sector.

摘要翻译： 在其中每个存储器单元具有耦合到位线的漏极的多扇区非易失性存储器阵列中，每个扇区的每个存储单元具有耦合到公共阵列源极线的源极，第一扇区的一行中的每个存储器单元具有 耦合到字线的控制栅极和另一扇区中的行的每个存储器单元具有耦合到该字线的控制栅极，用于对所述方法的一个扇区中的存储器单元进行编程的方法包括至少连接第二公共数组源极线 耦合到另一扇区中的存储器单元列的排列的每个位线，然后以正电压偏置公共阵列源极线和与另一扇区的列中的存储器单元的漏极耦合的位线，然后施加编程 电压被连接到第一扇区中所选择的单元的控制栅极的选定字线。 擦除方法包括将字线连接到参考电压，将至少一个未选择的公共阵列源线连接到耦合到取消选择的扇区中的存储器单元的列的排列的每个位线，然后以正电压偏置所选择的公共阵列 - 源极线和所述位线耦合到取消选择的扇区的列中的存储器单元的漏极，然后将正的擦除电压施加到所选择的扇区的所述公共阵列源极线。

公开(公告)号：US5265052A

公开(公告)日：1993-11-23

申请号：US909526

申请日：1992-06-29

申请人： Sebastiano D'Arrigo ,  Giuliano Imondi ,  Sung-Wei Lin ,  Gill Manzur

发明人： Sebastiano D'Arrigo ,  Giuliano Imondi ,  Sung-Wei Lin ,  Gill Manzur

IPC分类号： G11C8/08 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C8/08

摘要： A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising a positive voltage switching circuit, a first isolating transistor, and a second isolating transistor. The positive voltage switching circuit may include an inverter with feedback transistor and a third isolating transistor. In one embodiment, the positive voltage switching circuit is capable of switching up to three positive voltage values and reference voltage to the wordline terminal.

摘要翻译： 一种用于在包括正电压切换电路，第一隔离晶体管和第二隔离晶体管的浮动栅型EEPROM单元阵列中向字线施加读取，编程和擦除电压的电路。 正电压切换电路可以包括具有反馈晶体管的反相器和第三隔离晶体管。 在一个实施例中，正电压开关电路能够将最多三个正电压值和参考电压切换到字线端子。

公开(公告)号：US5177705A

公开(公告)日：1993-01-05

申请号：US402399

申请日：1989-09-05

申请人： David J. McElroy ,  Sebastiano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

发明人： David J. McElroy ,  Sebastiano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0425 ,  G11C16/10

摘要： A method is described for programming an array of EEPROM cells. Programming occurs through a Fowler-Nordheim tunnel window (34) between a source bitline (24) and a floating gate conductor (42) of a selected cell. The voltages applied to the control gate and to the source are selected to differ sufficiently to cause electrons to be drawn through the tunnel window (34) from the source region (24) to the floating gate conductor (42). The non-selected bitlines have a voltage impressed thereon that is of sufficient value to prevent inadvertent programming of cells in the selected row. The non-selected wordlines (48) have a voltage impressed thereon that is of sufficient value to prevent erasing of programmed non-selected cells.

摘要翻译： 描述了一种用于编程EEPROM单元阵列的方法。 编程通过位于选定单元的源位线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行。 选择施加到控制栅极和源极的电压以使其不同以使得电子从源极区域（24）通过隧道窗口（34）从浮动栅极导体（42）拉出。 未选择的位线具有施加在其上的电压，其具有足够的值以防止所选行中的单元的无意编程。 未选择的字线（48）具有其上施加的电压，其具有足够的值以防止编程的未选择单元的擦除。

公开(公告)号：US5060195A

公开(公告)日：1991-10-22

申请号：US595521

申请日：1990-10-11

申请人： Manzur Gill ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sung-Wei Lin

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7885

摘要： An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shaped drain region (16), with at corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (P1A). This floating gate channel section (32a/P1A) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the coresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD). The memory cell is programmed by hot carrier injection from the channel (18a) to the floating-gate channel section (32a), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel window section (34a) to the tunnel window subregion (15a).

摘要翻译： 在半导体衬底（11）的表面成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区域（14a）和形状的漏极区域（16），其间具有相应的沟道区域（18a）。 源区域（14a）的福勒 - 诺德海姆隧道窗口（15a）位于与通道（18a）相对的位置。 浮动栅极导体（FG）包括通道部分（32a）和隧道窗口部分（34a）。 浮栅导体形成为两级，第一级由第一级多晶硅（P1A）形成沟道段（32a）。 该浮动栅极沟道部分（32a / P1A）用作源极（14a）和漏极（16）区域的自对准注入掩模，使得沟道连接边缘与沟道部分的相应边缘对准。 控制栅极导体（CG）设置在浮动栅极导体（FG）上，由中间层间电介质（ILD）绝缘。 通过从信道（18a）到浮动栅极通道部分（32a）的热载流子注入来对存储器单元进行编程，并且通过Fowler-Nordheim从浮动栅极通道窗口部分（34a）向隧道窗口子区域（ 15a）。

公开(公告)号：US5010028A

公开(公告)日：1991-04-23

申请号：US458936

申请日：1989-12-29

申请人： Manzur Gill ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sung-Wei Lin

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7885

摘要： An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shared drain region (16), with a corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (PlA). This floating gate channel section (32a/PlA) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the corresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD). The memory cell is programmed by hot carrier injection from the channel (18a) to the floating-gate channel section (32a), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel window section (34a) to the tunnel window subregion (15a).

摘要翻译： 在半导体衬底（11）的表面成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区（14a）和共用漏极区（16），其间具有相应的沟道区（18a）。 源区域（14a）的福勒 - 诺德海姆隧道窗口（15a）位于与通道（18a）相对的位置。 浮动栅极导体（FG）包括通道部分（32a）和隧道窗口部分（34a）。 浮栅导体形成为两级，第一级由第一级多晶硅（PlA）形成沟道段（32a）。 该浮动栅极沟道部分（32a / P1A）用作源极（14a）和漏极（16）区域的自对准注入掩模，使得沟道结边缘与沟道部分的对应边缘对准。 控制栅极导体（CG）设置在浮动栅极导体（FG）上，由中间层间电介质（ILD）绝缘。 通过从信道（18a）到浮动栅极通道部分（32a）的热载流子注入来对存储器单元进行编程，并且通过Fowler-Nordheim从浮动栅极通道窗口部分（34a）向隧道窗口子区域（ 15a）。

公开(公告)号：US20080084773A1

公开(公告)日：2008-04-10

申请号：US11543338

申请日：2006-10-04

申请人： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

发明人： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

摘要翻译： 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。