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    Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths
    32.
    发明授权
    Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths 有权

    公开(公告)号：US09941881B1

    公开(公告)日：2018-04-10

    申请号：US15467943

    申请日：2017-03-23

    Applicant: QUALCOMM Incorporated

    Inventor： Changho Jung ,  Derek Yang ,  Sei Seung Yoon

    IPC: H03K19/20 ,  H03K19/003 ,  H03K19/0948

    CPC classification number: H03K19/00323 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0948 ,  H03K19/20

    Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

    Overlapping precharge and data write
    34.
    发明授权
    Overlapping precharge and data write 有权

    公开(公告)号：US09685210B1

    公开(公告)日：2017-06-20

    申请号：US15205857

    申请日：2016-07-08

    Applicant: QUALCOMM Incorporated

    Inventor： Sonia Ghosh ,  Changho Jung

    IPC: G11C7/12 ,  G11C11/419 ,  G11C7/06 ,  G06F12/00

    CPC classification number: G11C7/12 ,  G06F12/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1075 ,  G11C11/419 ,  G11C2207/002 ,  G11C2207/2209

    Abstract: A memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells. A precharge circuit precharges each of the plurality of bitlines before a read operation and precharges all but one of the plurality of bitlines following the read operation. A write driver drives the one of the plurality of bitlines following the read operation. A method includes precharging each of a plurality of bitlines before a read operation. Each of the plurality of bitlines is coupled to a corresponding one of a plurality of memory cells. The method further includes precharging all but one of the plurality of bitlines following the read operation and driving the one of the plurality of bitlines following the read operation.

    MEMORY WITH A SLEEP MODE
    35.
    发明申请
    MEMORY WITH A SLEEP MODE 审中-公开
    具有睡眠模式的记忆

    公开(公告)号：US20150310901A1

    公开(公告)日：2015-10-29

    申请号：US14261192

    申请日：2014-04-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： Changho Jung ,  Rakesh Vattikonda ,  Tony Chung Yiu Kwok

    IPC: G11C7/12 ,  G11C5/14

    CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C7/18 ,  G11C8/16 ,  G11C11/417

    Abstract: A memory and a method for operating the memory having a sleep mode are provided. The memory one or more storage elements and a bitline coupled to the one or more storage elements. A precharge circuit is configured to precharge the bitline during a precharge period and float the bitline during a sleep mode. An operating circuit coupled to the one or more storage elements, wherein at least one of the operating circuit and the one or more storage elements being configured to remain electrically coupled to a supply voltage in the sleep mode.

    Abstract translation: 提供了一种用于操作具有休眠模式的存储器的存储器和方法。 存储器一个或多个存储元件和耦合到一个或多个存储元件的位线。 预充电电路被配置为在预充电周期期间预充电位线，并且在睡眠模式期间浮动位线。 耦合到所述一个或多个存储元件的操作电路，其中所述操作电路和所述一个或多个存储元件中的至少一个被配置为在睡眠模式下保持电耦合到电源电压。

    PULSE GENERATOR
    36.
    发明申请
    PULSE GENERATOR 审中-公开
    脉冲发生器

    公开(公告)号：US20140355365A1

    公开(公告)日：2014-12-04

    申请号：US13910078

    申请日：2013-06-04

    Applicant: QUALCOMM Incorporated

    Inventor： Changho Jung ,  Nishith Desai ,  Chulmin Jung

    IPC: H03K3/037 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C8/08

    Abstract: Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method may include resetting a latch using feedback from a pulse generator by setting a latch using an input signal, triggering a pulse generator using an output from the latch, and resetting the latch using feedback from the pulse generator.

    Abstract translation: 公开了各种电路和操作电路的方法。 电路可以包括脉冲发生器和具有被配置为触发脉冲发生器的输出的锁存器，其中锁存器被配置为由输入信号设置并通过来自脉冲发生器的反馈进行复位。 方法可以包括使用来自脉冲发生器的反馈来使用来自脉冲发生器的反馈来重置锁存器，通过使用输入信号设置锁存器，使用来自锁存器的输出触发脉冲发生器，以及使用来自脉冲发生器的反馈来复位锁存器。

    Pseudo-NOR cell for ternary content addressable memory
    37.
    发明授权
    Pseudo-NOR cell for ternary content addressable memory 有权
    用于三进制内容可寻址存储器的伪NOR单元

    公开(公告)号：US08891273B2

    公开(公告)日：2014-11-18

    申请号：US13727494

    申请日：2012-12-26

    Applicant: QUALCOMM Incorporated

    Inventor： Rakesh Vattikonda ,  Nishith Desai ,  Changho Jung

    IPC: G11C15/00 ,  G11C15/04

    CPC classification number: G11C15/04

    Abstract: A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match.

    Abstract translation: 三元内容可寻址存储器（TCAM）内的方法包括从当前TCAM级的上拉晶体管的栅极处和当前TCAM的下拉晶体管的栅极处接收来自先前TCAM级的匹配线输出 阶段。 当从前一个TCAM级输出的匹配线指示不匹配时，该方法通过下拉晶体管将当前TCAM级的匹配线条设置为低值。 当从前一个TCAM级输出的匹配线指示匹配时，该方法还通过上拉晶体管将当前TCAM级的匹配线条设置为高值。

    APPARATUS AND METHOD FOR WRITING DATA TO MEMORY ARRAY CIRCUITS
    38.
    发明申请
    APPARATUS AND METHOD FOR WRITING DATA TO MEMORY ARRAY CIRCUITS 有权
    将数据写入存储阵列电路的装置和方法

    公开(公告)号：US20140269112A1

    公开(公告)日：2014-09-18

    申请号：US13863989

    申请日：2013-04-16

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

    Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

    Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

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