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    HIGH SPEED DEGLITCH SENSE AMPLIFIER
    32.
    发明申请
    HIGH SPEED DEGLITCH SENSE AMPLIFIER 审中-公开
    高速度感应放大器

    公开(公告)号：US20150294697A1

    公开(公告)日：2015-10-15

    申请号：US14251315

    申请日：2014-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Rui Li ,  David Li ,  Tahseen Shakir ,  Sei Seung Yoon

    IPC: G11C7/06 ,  G11C11/419

    CPC classification number: G11C7/065 ,  G11C11/419

    Abstract: A sense amplifier is provided that includes a skewed latch that latches a voltage difference developed responsive to a read operation on an accessed memory cell. The skewed latch includes a loaded logic gate that is cross-coupled with an unloaded logic gate. The loaded logic gate drives the unloaded logic gate and an output transistor whereas the unloaded logic gate drives only the loaded logic gate.

    Abstract translation: 提供了一种读出放大器，其包括倾斜的锁存器，其锁存响应于对所访问的存储器单元的读取操作产生的电压差。 偏斜锁存器包括与卸载逻辑门交叉耦合的加载逻辑门。 加载的逻辑门驱动无载逻辑门和输出晶体管，而无负载逻辑门仅驱动加载的逻辑门。

    Memory with double redundancy
    33.
    发明授权
    Memory with double redundancy 有权

    公开(公告)号：US12094528B2

    公开(公告)日：2024-09-17

    申请号：US17833852

    申请日：2022-06-06

    Applicant: QUALCOMM Incorporated

    Inventor： Dhvani Sheth ,  Hochul Lee ,  Anil Chowdary Kota ,  Chulmin Jung

    IPC: G11C29/14 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/418

    Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

    Write assist scheme with bitline
    34.
    发明授权
    Write assist scheme with bitline 有权

    公开(公告)号：US11488658B2

    公开(公告)日：2022-11-01

    申请号：US16862238

    申请日：2020-04-29

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Bin Liang ,  Chi-Jui Chen

    IPC: G11C11/4094 ,  G11C5/02 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4096

    Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

    Determining a voltage and/or frequency for a performance mode
    38.
    发明授权
    Determining a voltage and/or frequency for a performance mode 有权

    公开(公告)号：US11092646B1

    公开(公告)日：2021-08-17

    申请号：US16794105

    申请日：2020-02-18

    Applicant: QUALCOMM Incorporated

    Inventor： Sonia Ghosh ,  Changho Jung ,  Chulmin Jung

    IPC: G01R31/3181 ,  G01R31/317 ,  G01J1/18

    Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

    BYTE ENABLE MEMORY BUILT-IN SELF-TEST (MBIST) ALGORITHM
    39.
    发明申请
    BYTE ENABLE MEMORY BUILT-IN SELF-TEST (MBIST) ALGORITHM 审中-公开

    公开(公告)号：US20190115091A1

    公开(公告)日：2019-04-18

    申请号：US15964050

    申请日：2018-04-26

    Applicant: QUALCOMM Incorporated

    Inventor： Greg Seok ,  Fahad Ahmed ,  Chulmin Jung

    IPC: G11C29/44 ,  G11C29/10 ,  G11C29/18 ,  G11C29/16

    Abstract: A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

    High-speed level shifter
    40.
    发明授权
    High-speed level shifter 有权

    公开(公告)号：US09997208B1

    公开(公告)日：2018-06-12

    申请号：US15473124

    申请日：2017-03-29

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  Fahad Ahmed ,  Changho Jung ,  Sei Seung Yoon ,  David Li

    IPC: G11C8/08 ,  G11C5/14 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/12

    CPC classification number: G11C5/147 ,  G11C7/12 ,  G11C8/10 ,  H03K3/356069 ,  H03K19/018528

    Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

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