公开(公告)号：US5804486A

公开(公告)日：1998-09-08

申请号：US811616

申请日：1997-03-05

Applicant: Raffaele Zambrano ,  Giuseppe Fallico

Inventor： Raffaele Zambrano ,  Giuseppe Fallico

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/42304

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract translation: 高频双极晶体管结构包括形成在第二导电类型的硅层中的第一导电类型的基极区域，该基极区域包括被外部基极区域包围的本征基极区域，第二导电类型的发射极区域 形成在本征基区内，外基极区和发射极区分别与第一多晶硅层和第二多晶硅层接触。 第一和第二多晶硅层分别由基底金属电极和发射极金属电极接触。 在非本征基极区域和第一多晶硅层之间，提供硅化物层以降低双极晶体管的外部基极电阻。

公开(公告)号：US5777367A

公开(公告)日：1998-07-07

申请号：US927304

申请日：1997-09-11

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L23/62

CPC classification number: H01L29/7817 ,  H01L27/0255 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/1095 ,  H01L2924/0002

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages includes a plurality of serially connected diodes, each having a first and a second electrode, obtained in a lightly doped epitaxial layer of a first conductivity type in which the power device is also obtained; a first diode of said plurality of diodes has the first electrode connected to a gate layer of the power device and the second electrode connected to the second electrode of at least one second diode of the plurality whose first electrode is connected to a drain region of the power device; said first diode has its first electrode comprising a heavily doped contact region of the first conductivity type included in a lightly doped epitaxial layer region of the first conductivity type which is isolated from said lightly doped epitaxial layer by a buried region of a second conductivity type and by a heavily doped annular region of the second conductivity type extending from a semiconductor top surface to said buried region.

Abstract translation: 用于保护功率器件免于过电压的集成结构有源钳位包括多个串联连接的二极管，每个二极管具有第一和第二电极，其在第一导电类型的轻掺杂外延层中获得，其中功率器件也是 获得; 所述多个二极管的第一二极管具有连接到功率器件的栅极层的第一电极，并且第二电极连接到多个第二电极的至少一个第二二极管的第二电极，其第一电极连接到漏极区域 电源设备; 所述第一二极管具有包括第一导电类型的重掺杂接触区域的第一电极，所述第一导电类型的重掺杂接触区域包括在第一导电类型的轻掺杂外延层区域中，该区域通过第二导电类型的掩埋区域与所述轻掺杂外延层隔离， 通过从半导体顶表面延伸到所述掩埋区域的第二导电类型的重掺杂环形区域。

公开(公告)号：US5622876A

公开(公告)日：1997-04-22

申请号：US458083

申请日：1995-06-01

Applicant: Raffaele Zambrano ,  Sergio Palara

Inventor： Raffaele Zambrano ,  Sergio Palara

IPC: H01L27/06 ,  H01L2/265

CPC classification number: H01L27/0617

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1 , M2) together with vertically-conducting bipolar junction transistors transistors (T1, T2). These IGBT transistors are laterally conducting, having drain terminals (9, 19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1, T2) of the bipolar type.

Abstract translation: 一种适合功率应用的单片集成的晶体管桥式电路，包括至少一对IGBT晶体管（M1，M2）以及垂直导电的双极结型晶体管晶体管（T1，T2）。 这些IGBT晶体管是侧向导通的，具有形成在集成电路（1）的表面上的漏极端子（9,19），并且通过这些端子连接到双极型的另一对晶体管（T1，T2）。

公开(公告)号：US5591662A

公开(公告)日：1997-01-07

申请号：US471902

申请日：1995-06-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/088 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/70

CPC classification number: H01L21/823878 ,  H01L27/0922

Abstract: A PIC structure comprises a lightly doped semiconductor layer of a first conductivity type, superimposed over a heavily doped semiconductor substrate of the first conductivity type, wherein a power stage and a driving and control circuitry including first conductivity type-channel MOSFETs and second conductivity type-channel MOSFETs are integrated; the first conductivity type-channel and the second conductivity type-channel MOSFETs are provided inside second conductivity type and first conductivity type well regions, respectively, which are included in at least one isolated lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolation region of a second conductivity type.

Abstract translation: PIC结构包括叠加在第一导电类型的重掺杂半导体衬底上的第一导电类型的轻掺杂半导体层，其中功率级和驱动和控制电路包括第一导电类型沟道MOSFET和第二导电类型 - 沟道MOSFET集成; 第一导电类型沟道和第二导电类型沟道MOSFET分别设置在第二导电类型和第一导电类型阱区内，所述第一导电类型和第一导电类型阱区被包括在完全包围和隔离的第一导电类型的至少一个隔离的轻掺杂区域中 所述第一导电类型的轻掺杂层通过第二导电类型的相应隔离区域。

公开(公告)号：US5491357A

公开(公告)日：1996-02-13

申请号：US481198

申请日：1995-06-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/06 ,  H01L27/02 ,  H01L27/04 ,  H01L27/08 ,  H01L29/78

CPC classification number: H01L29/66712 ,  H01L27/0248 ,  H01L27/0288 ,  H01L29/7815

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device.

Abstract translation: 在用于功率MOS器件的集成结构感测电阻器中，包括从构成主电源器件的第一多个电池的至少一个电池的深体区域延伸到相应电池单元的深体区域的掺杂区域 构成电流感测装置的第二较小的多个单元。

公开(公告)号：US4898836A

公开(公告)日：1990-02-06

申请号：US341540

申请日：1989-04-21

Applicant: Raffaele Zambrano ,  Salvatore Musumeci

Inventor： Raffaele Zambrano ,  Salvatore Musumeci

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732

CPC classification number: H01L21/82285 ,  H01L21/761 ,  H01L27/0826

Abstract: In this process P+ type regions are diffused on a substrate of N type semiconductor meterial, said regions forming the horizontal isolation region of the NPN transistors and the low-resistivity collector region of the PNP transistors. Within each isolation region a high-concentration N+ type zone is created that acts as a low-resistivity collector region for the NPN transistors. An N type epitaxial layer is then grown over the whole surface of the device. The completion of the device is carried out in such a way to ensure that the low-concentration collector thickness of transistors NPN be practically equal to the low-concentration collector thickness of transistors PNP.

公开(公告)号：US07052985B2

公开(公告)日：2006-05-30

申请号：US10804492

申请日：2004-03-18

Applicant: Raffaele Zambrano ,  Cesare Artoni ,  Chiara Corvasce

Inventor： Raffaele Zambrano ,  Cesare Artoni ,  Chiara Corvasce

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L27/11502 ,  H01L21/76877

Abstract: A process forms an integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract translation: 一种方法形成一种集成装置，其具有：第一导电区域; 第二导电区域; 布置在第一和第二导电区域之间的绝缘层; 至少一个通孔，其延伸在所述第一和第二导电区域之间的绝缘层中; 以及形成在所述通孔中并且电连接所述第一导电区域和所述第二导电区域的接触结构。 接触结构由覆盖通孔的侧表面和底部的导电材料层形成，并且包围由第二导电区域封闭在顶部的空区域。 导电材料层优选地包括彼此顶部布置的钛层和氮化钛层。

公开(公告)号：US07049646B2

公开(公告)日：2006-05-23

申请号：US10327704

申请日：2002-12-20

Applicant: Raffaele Zambrano ,  Cesare Artoni

Inventor： Raffaele Zambrano ,  Cesare Artoni

IPC: H01L29/76

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

公开(公告)号：US06420765B1

公开(公告)日：2002-07-16

申请号：US09875448

申请日：2001-06-05

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L31119

CPC classification number: G11C17/12

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P−. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

Abstract translation: 通过目视检查不能解码的ROM存储单元包括具有第一导电类型，特别是P-的半导体材料的衬底。 具有第一阈值电压的第一MOS器件形成在衬底的第一部分中，并且具有大于第一阈值电压的第二阈值电压的MOS器件形成在与第一部分相邻的衬底的第二部分中 。 第二MOS器件是在ROM存储器单元的读取阶段期间被反向偏置的二极管，并且包括具有第一导电类型的源极区域和具有第二导电类型的漏极区域。 源区具有高于衬底的掺杂水平。

公开(公告)号：US06326271B2

公开(公告)日：2001-12-04

申请号：US09746789

申请日：2000-12-21

Applicant: Angelo Magri' ,  Raffaele Zambrano ,  Ferruccio Frisina

Inventor： Angelo Magri' ,  Raffaele Zambrano ,  Ferruccio Frisina

IPC: H01L21336

CPC classification number: H01L29/7802 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

Abstract: A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes of a second conductivity type formed in the semiconductor layer under the elongated openings, source regions of the first conductivity type included in the body stripes and a metal layer covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion including a source region extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions, longitudinally intercalated with the first portions, substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions and second portions of the body stripes being respectively aligned in a direction transversal to the longitudinal axis.