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公开(公告)号：US07122455B1
公开(公告)日：2006-10-17
申请号：US10790567
申请日：2004-03-01
申请人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
发明人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , Y10S438/942 , Y10S438/947
摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.
摘要翻译： 为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。 此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。 不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。
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32.发明申请Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions 失效用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法公开(公告)号：US20060121711A1
公开(公告)日：2006-06-08
申请号：US11002586
申请日：2004-12-03
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/32139 , H01L29/66628 , H01L29/66659
摘要： A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
摘要翻译： 在多晶硅栅电极上形成特定尺寸的间隔物的方法在选择性外延生长期间保护多晶硅栅电极的侧壁。 无论是不对称的还是对称的，通过在限定多晶硅栅电极图案和图案中使用相同的特定曝光工具（例如193nm波长步长和扫描曝光工具）和相同的图案掩模版来精确限定 间隔件，同时采用紧密对准规格。
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公开(公告)号：US06960804B1
公开(公告)日：2005-11-01
申请号：US10633034
申请日：2003-10-10
IPC分类号： H01L21/027 , H01L21/336 , H01L29/786 , H01L29/788
CPC分类号： H01L29/785 , H01L21/0276 , H01L29/42392 , H01L29/66795
摘要： A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.
摘要翻译： 双半导体器件包括衬底，绝缘层，鳍和栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 翅片具有多个侧表面，顶表面和底表面。 栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。 用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。
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公开(公告)号：US06921963B2
公开(公告)日：2005-07-26
申请号：US10830006
申请日：2004-04-23
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/06
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66818 , H01L29/78687
摘要： A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.
摘要翻译： 这里描述了窄通道FinFET，其具有窄的通道宽度。 可以在窄通道上形成保护层，保护层比窄通道宽。
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35.发明申请公开(公告)号：US20050146059A1
公开(公告)日：2005-07-07
申请号：US10747680
申请日：2003-12-30
IPC分类号： H01L21/266 , H01L21/336 , H01L27/088
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/6656
摘要： A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.
摘要翻译： 半导体器件及其制造方法通过在衬底和栅电极上沉积间隔层形成间隔物并在间隔层上形成保护层。 干蚀刻保护层以在间隔层上留下薄膜侧壁。 然后蚀刻间隔层，其中保护层保护间隔层的外侧壁。 该蚀刻在栅极上产生具有平行于栅电极侧壁延伸的基本垂直侧壁的间隔物。 间隔物的I形形状在源/漏离子注入过程中防止穿通，从而提供改进的源极/漏极注入剂量分布。
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36.发明授权Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material 失效在无定形碳和ARC材料之间具有渐变过渡的无定形碳ARC叠层的形成公开(公告)号：US06875664B1
公开(公告)日：2005-04-05
申请号：US10230794
申请日：2002-08-29
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/312 , H01L21/314 , H01L21/3213 , H01L21/336
CPC分类号： H01L21/3145 , H01L21/02115 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/312 , H01L21/3144 , H01L21/3146 , H01L21/32139
摘要： A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.
摘要翻译： 使用无定形碳硬掩模形成集成电路的方法包括在导电材料层之上提供无定形碳材料层，并在无定形碳材料上方提供抗反射涂层（ARC）材料层。 在无定形碳材料层和ARC材料层之间形成过渡区域。 过渡区域具有提供无定形碳材料层和ARC材料层之间的转变的浓度分布。 去除非晶碳材料层，ARC材料层和过渡区域的一部分以形成硬掩模，并且根据硬掩模在导电材料层中形成特征。
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公开(公告)号：US06864164B1
公开(公告)日：2005-03-08
申请号：US10320536
申请日：2002-12-17
IPC分类号： H01L21/336 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method of forming a gate electrode for a fin field effect transistor (FinFET) includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a carbon layer over the oxide layer and forming a trench in the oxide layer and the carbon layer, where the trench crosses over the fin. The method also includes filling the trench with a material to form the gate electrode.
摘要翻译： 形成鳍状场效应晶体管（FinFET）的栅电极的方法包括在衬底上形成翅片并在鳍上形成氧化物层。 所述方法还包括在所述氧化物层上形成碳层并在所述氧化物层和所述碳层中形成沟槽，其中所述沟槽跨过所述鳍片。 该方法还包括用材料填充沟槽以形成栅电极。
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公开(公告)号：US06855582B1
公开(公告)日：2005-02-15
申请号：US10459589
申请日：2003-06-12
IPC分类号： H01L21/00 , H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66818 , H01L29/78642
摘要： A method of forming a gate electrode for a fin field effect transistor (FinFET) is provided. The method includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a trench in the oxide layer, the trench crossing over the fin, and filling the trench with a material to form a gate electrode.
摘要翻译： 提供一种形成鳍状场效应晶体管（FinFET）的栅电极的方法。 该方法包括在衬底上形成翅片并在翅片上形成氧化物层。 该方法还包括在氧化物层中形成沟槽，沟槽穿过翅片，并用材料填充沟槽以形成栅电极。
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公开(公告)号：US20050020019A1
公开(公告)日：2005-01-27
申请号：US10922093
申请日：2004-08-19
申请人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
发明人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L21/3205
CPC分类号： H01L29/66477 , H01L21/28123 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所得到的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。
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40.发明授权Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance 有权使用具有改善的耐蚀性的非晶碳制造半导体器件的方法公开(公告)号：US06750127B1
公开(公告)日：2004-06-15
申请号：US10367407
申请日：2003-02-14
申请人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
发明人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337
摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。
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