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公开(公告)号：US20100207657A1
公开(公告)日：2010-08-19
申请号：US12773055
申请日：2010-05-04
IPC分类号： H03K19/195
CPC分类号： H03K19/1954 , B82Y10/00 , G06N99/002 , H03K17/92 , H03K19/0008 , H03K19/1952 , H03K2217/0036
摘要： In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.
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公开(公告)号：US07170960B2
公开(公告)日：2007-01-30
申请号：US10324633
申请日：2002-12-20
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H04L7/00
CPC分类号： H03L7/24 , H03K19/195 , H04L7/027 , H04L7/0276
摘要： A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.
摘要翻译： 一种用于超导体系统的时钟恢复电路（10），其能够使系统时钟的相位瞬间复位而无需任何脉冲相互作用。 时钟恢复电路（10）包括长度为2T的约瑟夫逊传输线路振荡器环路（14），其中T等于一个时钟周期。 第一和第二数据输入（16,18）用于将数据脉冲注入振荡器回路（14）。 脉冲发生器（24）用于将初始时钟脉冲注入作为周期性时钟信号输出的振荡器环路（14）。 输出抽头（12）用于从第一和第二数据输入（16,18）之一输出数据脉冲，并且在没有数据脉冲的情况下输出周期性时钟信号。 当在第一和第二输出抽头（32,34）之一上输入数据脉冲时，时钟相位被瞬时复位。
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公开(公告)号：US06836141B2
公开(公告)日：2004-12-28
申请号：US10410923
申请日：2003-04-11
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H03K19195
CPC分类号： G11C11/44
摘要： A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.
摘要翻译： 超导体存储器阵列（10）具有高关联吞吐量，具有低功耗和简单的架构。 超导体存储器阵列（10）包括以列 - 列格式布置的每个存储单元（12a-12d），每个存储单元包括用于存储二进制值的约瑟夫逊结（16a-16d）的存储环路（14a-14d）。 行地址线（24a，24b）各自与存储器单元（12a-12d）的一行串联磁耦合，并且列地址线（26a，26b）各自串联连接到存储单元（12a）的列 -12d）。 读出放大器（38a，38b）位于每个列地址线（26a，26b）上，用于在由行地址线读信号发起的READ操作期间感测位于列中的存储单元（12a-12d）中的状态变化 。
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34.发明授权Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits 有权用于在超导体集成电路中通过接地平面边界进行信号传播的电容器公开(公告)号：US06777808B2
公开(公告)日：2004-08-17
申请号：US10293944
申请日：2002-11-12
IPC分类号： H01L2906
CPC分类号： H01L27/18 , H01L2924/0002 , H01L2924/00
摘要： The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
摘要翻译： 在超导体集成电路（图1）中与电容A52相关联的自感通过在电容器上方添加一层超导体金属（A54）来减少，有效地产生负电感以抵消电容器引线的自感， 从而降低电路的电感。 因此，可能通过电容器传输单通量量子（“SFQ”）脉冲。 上述类型的电容器（19和25图5）被并入超导集成电路SFQ传输线（图5）中，以允许SFQ脉冲的SQUID到SQUID传输，同时将相应SQUID的电路接地保持在DC 隔离。 偏置电流（10）可以连续地提供给多个SQUID（图1和图3，图7和图9），减少了先前为多个SQUID的操作所需的电源电流。
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公开(公告)号：US06452520B1
公开(公告)日：2002-09-17
申请号：US09725620
申请日：2000-11-29
IPC分类号： H03M100
CPC分类号： H03M1/0602 , H03M1/60
摘要： A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).
摘要翻译： 超导A / D转换器（10）具有用于消除主量化器（30）中的非线性的误差校正系统（70）。 转换器（10）包括主量化器（30），主SFQ计数器（50）和纠错系统（70）。 主量化器（30）基于模拟输入信号的平均电压产生初始SFQ脉冲。 主SFQ计数器（50）基于主SFQ脉冲的频率将初级SFQ脉冲转换成数字输出信号。 误差校正系统（70）根据模拟输入信号和初级SFQ脉冲校正数字输出信号。 使用主SFQ脉冲来校正数字输出信号允许转换器（10）考虑主量化器（30）的非线性。
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公开(公告)号：US11417821B2
公开(公告)日：2022-08-16
申请号：US16296007
申请日：2019-03-07
摘要： Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.
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公开(公告)号：US09455707B2
公开(公告)日：2016-09-27
申请号：US14325518
申请日：2014-07-08
申请人： Anna Y. Herr , Quentin P. Herr
发明人： Anna Y. Herr , Quentin P. Herr
IPC分类号： H03K19/00 , H03K19/195 , G11C11/44 , H03K3/38 , B82Y10/00
CPC分类号： H03K19/0008 , B82Y10/00 , G06N99/002 , G11C11/44 , H03K3/38 , H03K19/1952
摘要： One embodiment includes a superconductive gate system. The superconductive gate system includes a Josephson D-gate circuit comprising a bi-stable loop configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum (SFQ) pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input. The digital state can be provided at an output. The readout circuit is coupled to the output and can be configured to reproduce the digital state as an output signal.
摘要翻译： 一个实施例包括超导门系统。 超导栅极系统包括约瑟夫森D门电路，其包括双稳态环路，其被配置为响应于在第一数据状态和第二数据状态上提供的使能单通量量子（SFQ）脉冲而将数字状态存储为第一数据状态和第二数据状态之一 启用输入和相应的存在或不存在在数据输入上提供的数据SFQ脉冲。 数字状态可以在输出端提供。 读出电路耦合到输出，并且可以被配置为将数字状态再现为输出信号。
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公开(公告)号：US20110267878A1
公开(公告)日：2011-11-03
申请号：US12771454
申请日：2010-04-30
申请人： Anna Y. Herr , Quentin P. Herr
发明人： Anna Y. Herr , Quentin P. Herr
CPC分类号： G11C11/44
摘要： One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state corresponding to one of a binary logic-1 state and a binary logic-0 state in response to a word-write current that is provided on a word-write line and a bit-write current that is provided on a bit-write line. The HMJJD is also configured to output the respective digital state in response to a word-read current that is provided on a word-read line and a bit-read current that is provided on a bit-read line.
摘要翻译： 本发明的一个方面包括约瑟夫森磁随机存取存储器（JMRAM）系统。 该系统包括以行和列排列的存储单元阵列。 每个存储器单元包括HMJJD，其被配置为响应于在字写入线上提供的字写入电流来存储对应于二进制逻辑1状态和二进制逻辑0状态之一的数字状态 以及在位写入线路上提供的位写入电流。 HMJJD还被配置为响应于在字读取线上提供的字读电流和提供在位读取线上的位读电流来输出相应的数字状态。
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公开(公告)号：US20100033252A1
公开(公告)日：2010-02-11
申请号：US12186465
申请日：2008-08-05
IPC分类号： H03F3/60
摘要： The disclosure generally relates to a method and apparatus for providing high-speed, low signal power amplification. In an exemplary embodiment, the disclosure relates to a method for providing a wideband amplification of a signal by forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines.
摘要翻译： 本公开一般涉及用于提供高速，低信号功率放大的方法和装置。 在示例性实施例中，本发明涉及一种用于通过与第二传输线并联形成第一传输线来提供信号的宽带放大的方法，所述第一传输线和第二传输线中的每一条具有多个超导传输 每个传输线具有传输线延迟; 在第一传输线和第二传输线之间插入多个放大级，每个放大级具有谐振电路延迟的谐振电路; 并且使所述多个放大级中的至少一个的所述谐振电路延迟与至少一个超导传输线的传输线延迟基本匹配。
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公开(公告)号：US20100026538A1
公开(公告)日：2010-02-04
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/02
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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