公开(公告)号：US20170287802A1

公开(公告)日：2017-10-05

申请号：US15430455

申请日：2017-02-11

Applicant: Renesas Electronics Corporation

Inventor： Hideo NUMABE ,  Koji TATENO ,  Yusuke OJIMA ,  Yoshihiko YOKOI ,  Shinya ISHIDA ,  Hitoshi MATSUURA

IPC: H01L23/34 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/265 ,  H01L21/3205 ,  H03K17/16 ,  H01L49/02

CPC classification number: H01L23/34 ,  H01L21/26513 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/823412 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/53271 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/7393 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H03K17/16 ,  H03K2017/0806 ,  H03K2217/0027 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.

公开(公告)号：US20170054010A1

公开(公告)日：2017-02-23

申请号：US15180988

申请日：2016-06-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/10 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66348

Abstract: To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.

Abstract translation: 实现了具有低导通电压和高负载短路耐受沟槽栅极IGBT的半导体器件。 半导体衬底的背面上的集电极区域由相对轻掺杂的P +型第一集电极区域和相对高掺杂的P ++型第二集电极区域构成。 P ++型第二集电极区域在平面图中包括在其中具有第一线性沟槽栅极电极的第一沟槽和形成在第一沟槽的侧表面上的N +型发射极区域之间以及在其中具有第二线性栅极的第二沟槽之间的界面 沟槽栅极电极和形成在第二沟槽的侧表面上的N +型发射极区域。 这使得从半导体衬底的表面侧注入的电子能够到达P ++型的第二集电极区域，并且与半导体衬底的背面侧注入空穴。

公开(公告)号：US20160365433A1

公开(公告)日：2016-12-15

申请号：US15151112

申请日：2016-05-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7396 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in a hybrid sub-cell region and an inactive cell region, and a contact trench penetrating it. Also, the contact trench is divided in a crossing region of extending directions of the hybrid sub-cell region and the emitter coupling section. Further, an n+-type emitter region is disposed so as to be apart from an end of the divided contact trench. With such configuration of not forming the contact trench in the crossing region, the working failure of the contact trench can be reduced. Also, because the n+-type emitter region is disposed so as to be apart from the end of the contact trench, the breakdown resistance of the semiconductor device can be improved.

Abstract translation: 半导体器件包括沟槽栅极电极，将它们彼此耦合的发射极耦合部分，布置在混合子电池区域中的层间绝缘膜和非活性电池区域以及穿透其的接触沟槽。 此外，接触沟槽被划分为混合子电池区域和发射极耦合部分的延伸方向的交叉区域。 此外，n +型发射极区域设置成与分开的接触沟槽的一端分开。 通过在交叉区域中不形成接触沟槽的这种构造，可以减小接触沟槽的工作故障。 此外，由于n +型发射极区域配置成离开接触沟槽的端部，所以可以提高半导体器件的击穿电阻。

公开(公告)号：US20240088275A1

公开(公告)日：2024-03-14

申请号：US18353261

申请日：2023-07-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masafumi HIROSE ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/66348

Abstract: Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.

公开(公告)号：US20230231042A1

公开(公告)日：2023-07-20

申请号：US18055635

申请日：2022-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0657 ,  H01L29/861 ,  H01L29/66348

Abstract: A reliability of a semiconductor device is ensured, and performance of the device is improved. A semiconductor device including a region 1A and a region 2A includes an n-type semiconductor substrate TS having a front surface BS1, BS2 and a back surface SUB, a IGBT formed on a semiconductor substrate in a region 1A, and a diode formed on the semiconductor substrate SUB in a region 2A. And a thickness T1 of the semiconductor substrate SUB in the region 1A is smaller than a thickness of the semiconductor substrate T2 in the region 2A.

公开(公告)号：US20190157439A1

公开(公告)日：2019-05-23

申请号：US16256635

申请日：2019-01-24

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n−-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n−-type drift region is used as the reverse transfer capacitance.

公开(公告)号：US20180182875A1

公开(公告)日：2018-06-28

申请号：US15798218

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Ryo KANDA ,  Hitoshi MATSUURA ,  Shuichi KIKUCHI

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/4238

Abstract: A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).

公开(公告)号：US20170154985A1

公开(公告)日：2017-06-01

申请号：US15429286

申请日：2017-02-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

公开(公告)号：US20170117396A1

公开(公告)日：2017-04-27

申请号：US15298958

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/49 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6634 ,  H01L29/66348

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n−-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n−-type drift region is used as the reverse transfer capacitance.

公开(公告)号：US20160359026A1

公开(公告)日：2016-12-08

申请号：US15151094

申请日：2016-05-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/36 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66348

Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.

Abstract translation: 提供了包括具有低导通状态电压和低关断损耗特征的IGBT元件的半导体器件。 半导体器件由沟槽栅型IGBT元件构成。 IGBT元件包括：施加栅极电位的多个栅极沟槽电极; 以及给予发射极电位的多个发射极沟槽电极。 在相邻的沟槽电极之间形成与发射极电极层的接触。 在这方面，在半导体衬底中形成P型浮动区，该P型浮动区通过层间绝缘层与至少一些发射极沟槽电极的底部接触。