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    Memory arrays and methods of forming memory cells
    32.
    发明授权
    Memory arrays and methods of forming memory cells 有权

    公开(公告)号：US08546231B2

    公开(公告)日：2013-10-01

    申请号：US13298962

    申请日：2011-11-17

    Applicant: Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    Inventor： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    IPC: G11C17/16

    CPC classification number: H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

    Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

    PHASE CHANGE MEMORY CELL AND MANUFACTURING METHOD THEREOF USING MINITRENCHES
    35.
    发明申请
    PHASE CHANGE MEMORY CELL AND MANUFACTURING METHOD THEREOF USING MINITRENCHES 有权
    相变存储器单元及其使用MINITRENCHES的制造方法

    公开(公告)号：US20110237045A1

    公开(公告)日：2011-09-29

    申请号：US13158291

    申请日：2011-06-10

    Applicant: Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    Inventor： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC: H01L21/20

    CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

    Phase change memory cell and manufacturing method thereof using minitrenches
    36.
    发明授权
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元及其制造方法

    公开(公告)号：US07993957B2

    公开(公告)日：2011-08-09

    申请号：US11045170

    申请日：2005-01-27

    Applicant: Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    Inventor： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC: H01L21/00

    CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

    Self-aligned bipolar junction transistors
    37.
    发明授权
    Self-aligned bipolar junction transistors 有权
    自对准双极结型晶体管

    公开(公告)号：US07875513B2

    公开(公告)日：2011-01-25

    申请号：US11411311

    申请日：2006-04-26

    Applicant: Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    Inventor： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    IPC: H01L21/82338

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

    Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

    Abstract translation: 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

    Process for self-aligned manufacture of integrated electronic devices
    38.
    发明授权
    Process for self-aligned manufacture of integrated electronic devices 有权
    集成电子设备的自对准制造工艺

    公开(公告)号：US07772084B2

    公开(公告)日：2010-08-10

    申请号：US12006706

    申请日：2008-01-04

    Applicant: Roberto Bez ,  Alessandro Grossi

    Inventor： Roberto Bez ,  Alessandro Grossi

    IPC: H01L21/76

    CPC classification number: H01L21/76232 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

    Abstract: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

    Abstract translation: 一种用于集成电子器件的自对准制造的方法包括：在具有衬底的半导体晶片中形成限定有源区并从衬底突出的绝缘结构; 形成第一导电层，其涂覆绝缘结构和有源区; 并部分地去除第一导电层。 此外，在形成所述第一导电层之前，在绝缘结构中形成凹部。

    Self-aligned biopolar junction transistors
    39.
    发明申请
    Self-aligned biopolar junction transistors 有权
    自对准生物极结结晶体管

    公开(公告)号：US20070254446A1

    公开(公告)日：2007-11-01

    申请号：US11411311

    申请日：2006-04-26

    Applicant: Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    Inventor： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    IPC: H01L29/80 ,  H01L21/331

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

    Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

    Abstract translation: 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured
    40.
    发明申请
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured 有权
    因此制造Cu-damascene技术和相变存储器阵列中的相变存储器阵列的制造方法

    公开(公告)号：US20070148814A1

    公开(公告)日：2007-06-28

    申请号：US11317622

    申请日：2005-12-22

    Applicant: Fabio Pellizzer ,  Roberto Bez ,  Maria Marangon ,  Roberta Piva ,  Laura Aina

    Inventor： Fabio Pellizzer ,  Roberto Bez ,  Maria Marangon ,  Roberta Piva ,  Laura Aina

    IPC: H01L21/06

    CPC classification number: H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

    Abstract translation: 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。

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