公开(公告)号：US20140021590A1

公开(公告)日：2014-01-23

申请号：US13552014

申请日：2012-07-18

申请人： Hans-Joachim Schulze ,  Johannes Laven ,  Dieter Fuchs ,  Werner Schustereder ,  Roman Knoefler

发明人： Hans-Joachim Schulze ,  Johannes Laven ,  Dieter Fuchs ,  Werner Schustereder ,  Roman Knoefler

IPC分类号： H01L29/06 ,  H01L21/04

CPC分类号： H01L29/0619 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611

摘要： A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics.

摘要翻译： 制造方法为半导体器件提供衬底层和与衬底层相邻的外延层。 外延层包括不同导电类型的第一列和第二列。 第一和第二列沿着主晶体方向延伸，沿着主晶体方向，注入离子的沟道从第一表面发生到外延层中。 第一和第二列之一的垂直掺杂剂分布包括由第二部分分开的第一部分。 在第一部分中，掺杂剂浓度变化至多30％。 在第二部分中，掺杂剂浓度低于第一部分。 第一部分的总长度与第一和第二部分的总长度之比至少为50％。 均匀的掺杂剂分布提高了器件特性。

公开(公告)号：US08399325B2

公开(公告)日：2013-03-19

申请号：US13240308

申请日：2011-09-22

申请人： Hans Weber ,  Stefan Gamerith ,  Roman Knoefler ,  Kurt Sorschag ,  Anton Mauder

发明人： Hans Weber ,  Stefan Gamerith ,  Roman Knoefler ,  Kurt Sorschag ,  Anton Mauder

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803

摘要： A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure.

摘要翻译： 一种用于制造具有电极结构的半导体器件的方法，包括：提供具有第一表面的半导体本体，以及从所述第一表面沿着所述半导体本体的垂直方向延伸的第一牺牲层，以及形成从所述第一表面延伸的第一沟槽 表面进入半导体体。 至少通过在与第一表面相邻的部分中去除牺牲层来形成第一沟槽。 该方法还包括通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽，形成覆盖第二沟槽侧壁的电介质层，以及在第二沟槽，电极和电介质层中的电介质层上形成电极 在形成电极结构的第二沟槽中。

公开(公告)号：US20130005099A1

公开(公告)日：2013-01-03

申请号：US13537374

申请日：2012-06-29

申请人： Hans Weber ,  Franz Hirler ,  Andreas Meiser ,  Anton Mauder ,  Kurt Sorschag ,  Stefan Gamerith ,  Roman Knoefler

发明人： Hans Weber ,  Franz Hirler ,  Andreas Meiser ,  Anton Mauder ,  Kurt Sorschag ,  Stefan Gamerith ,  Roman Knoefler

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7828

摘要： A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.

摘要翻译： 具有电介质层的半导体器件通过向半导体本体提供延伸到半导体本体中的第一沟槽，第一沟槽具有底部和侧壁来制造。 第一电介质层形成在第一沟槽的下部的侧壁上，第一插塞形成在第一沟槽的下部，以覆盖第一电介质层。 第一个塞子留下未覆盖的侧壁的上部。 牺牲层形成在第一沟槽的上部的侧壁上，第二插塞形成在第一沟槽的上部。 除去牺牲层以形成具有侧壁和底部的第二沟槽。 第二介电层形成在第二沟槽中并延伸到第一介电层。

公开(公告)号：US20120083085A1

公开(公告)日：2012-04-05

申请号：US13240308

申请日：2011-09-22

申请人： Hans Weber ,  Stefan Gamerith ,  Roman Knoefler ,  Kurt Sorschag ,  Anton Mauder

发明人： Hans Weber ,  Stefan Gamerith ,  Roman Knoefler ,  Kurt Sorschag ,  Anton Mauder

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803

摘要： A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure.

摘要翻译： 一种用于制造具有电极结构的半导体器件的方法，包括：提供具有第一表面的半导体本体，以及从所述第一表面沿着所述半导体本体的垂直方向延伸的第一牺牲层，以及形成从所述第一表面延伸的第一沟槽 表面进入半导体体。 至少通过在与第一表面相邻的部分中去除牺牲层来形成第一沟槽。 该方法还包括通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽，形成覆盖第二沟槽侧壁的电介质层，以及在第二沟槽，电极和电介质层中的电介质层上形成电极 在形成电极结构的第二沟槽中。

公开(公告)号：US20100297818A1

公开(公告)日：2010-11-25

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US07800182B2

公开(公告)日：2010-09-21

申请号：US11602117

申请日：2006-11-20

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L23/62

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US07678704B2

公开(公告)日：2010-03-16

申请号：US11301515

申请日：2005-12-13

申请人： Veit Klee ,  Roman Knoefler ,  Uwe Paul Schroeder

发明人： Veit Klee ,  Roman Knoefler ,  Uwe Paul Schroeder

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

摘要翻译： 为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。 图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。 掩模材料形成在绝缘层上并与图案转印层对准。 去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。

公开(公告)号：US07488670B2

公开(公告)日：2009-02-10

申请号：US11180432

申请日：2005-07-13

申请人： Roman Knoefler ,  Armin Tilke

发明人： Roman Knoefler ,  Armin Tilke

IPC分类号： H01L21/322 ,  H01L21/425

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L29/7833 ,  H01L29/7848

摘要： An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.

摘要翻译： 本发明的实施例提供半导体制造方法。 该方法包括在半导体器件中形成应变通道区域。 实施例包括在制造的中间阶段在半导体器件的非晶部分上形成应力层。 该器件被掩蔽，并且应力层的一部分中的应变被放宽。 重结晶中间装置的非晶部分将应变从应力器传递到基底。 通过随后的器件制造，至少一部分菌株保留在衬底中，从而改善了完成的器件的性能。 在其它实施例中，在装置的第一部分上形成拉伸应力层，并且在第二部分上形成压应力层。 拉伸应力层在PMOS器件中形成压缩通道，并且压应力器在NMOS器件中形成拉伸通道。

公开(公告)号：US20080261395A1

公开(公告)日：2008-10-23

申请号：US11738086

申请日：2007-04-20

申请人： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

发明人： Stefan Blawid ,  Ludovic Lattard ,  Roman Knoefler ,  Manuela Gutsch ,  David Pritchard ,  Martin Roessiger

IPC分类号： H01L23/48 ,  G03F1/00 ,  H01L21/44

CPC分类号： H01L27/0203 ,  H01L27/105 ,  H01L27/115

摘要： Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

摘要翻译： 具有第一结构的半导体器件包括多个至少部分平行的线性结构，第二结构包括多个衬垫结构，至少部分地形成一组直线结构，弯曲结构，分段线性结构和分段弯曲 结构，其与第一结构成角度定位，并且多个垫结构在第一结构中与至少一个线性结构相交。 还包括具有至少一个半导体器件的电子器件，用于制造半导体器件的方法和掩模系统。

公开(公告)号：US07217619B2

公开(公告)日：2007-05-15

申请号：US10954157

申请日：2004-09-29

申请人： Roman Knoefler

发明人： Roman Knoefler

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： The top of the semiconductor body (1) has a sacrificial layer (4) made of nitride applied to it on a region, which is provided for the actuation circuit. A memory layer (6) provided for the memory cells is applied over the entire area and is removed above the sacrificial layer (4) by dry etching. The nitride in the sacrificial layer (4) can then be removed by wet chemical means without starting to etch the semiconductor material.

摘要翻译： 半导体本体（1）的顶部具有由施加到其上的氮化物制成的牺牲层（4），该区域被设置用于致动电路。 提供给存储单元的存储层（6）被施加在整个区域上，并且通过干蚀刻在牺牲层（4）上去除。 然后可以通过湿式化学方法去除牺牲层（4）中的氮化物，而不开始蚀刻半导体材料。