公开(公告)号：US20110116321A1

公开(公告)日：2011-05-19

申请号：US13008448

申请日：2011-01-18

申请人： Takeshi AGARI ,  Hirotoshi Sato ,  Kiyoyasu Akai ,  Minoru Senda ,  Hiroaki Nakai

发明人： Takeshi AGARI ,  Hirotoshi Sato ,  Kiyoyasu Akai ,  Minoru Senda ,  Hiroaki Nakai

IPC分类号： G11C16/30 ,  G11C5/14

CPC分类号： G11C5/14 ,  G11C5/148 ,  G11C8/08 ,  G11C8/10 ,  G11C11/417

摘要： When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

摘要翻译： 当操作模式转换到待机模式时，第一晶体管通过控制信号进入导通状态，并且字线由此被钳位到接地电压。 此外，第二晶体管进入非导通状态，并且切断向字线驱动器提供内部电源电压。 随后，停止内部电源电压的供应以节省电力。 当操作模式返回到正常模式时，内部电源电压的供应开始，随后通过控制信号使第一晶体管变为非导通状态，从而使第二晶体管进入导通状态 州。

公开(公告)号：US07826298B2

公开(公告)日：2010-11-02

申请号：US12153308

申请日：2008-05-16

申请人： Hiroaki Nakai ,  Hirotoshi Sato ,  Kiyoyasu Akai

发明人： Hiroaki Nakai ,  Hirotoshi Sato ,  Kiyoyasu Akai

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C5/147

摘要： In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.

摘要翻译： 在根据本发明的SRAM中，用于存储单元的内部电源电压被施加到包括在均衡器，写入驱动器和列选择栅极中的每个P沟道MOS晶体管的背栅极。 因此，即使关闭外围电路的内部电源电压来降低待机时的电流消耗，所以每个P沟道MOS晶体管的阈值电压保持在高电平，因此漏电流小。

公开(公告)号：US20080291754A1

公开(公告)日：2008-11-27

申请号：US12153308

申请日：2008-05-16

申请人： Hiroaki Nakai ,  Hirotoshi Sato ,  Kiyoyasu Akai

发明人： Hiroaki Nakai ,  Hirotoshi Sato ,  Kiyoyasu Akai

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C11/412 ,  G11C5/147

摘要： In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.

摘要翻译： 在根据本发明的SRAM中，用于存储单元的内部电源电压被施加到包括在均衡器，写入驱动器和列选择栅极中的每个P沟道MOS晶体管的背栅极。 因此，即使关闭外围电路的内部电源电压来降低待机时的电流消耗，所以每个P沟道MOS晶体管的阈值电压保持在高电平，因此漏电流小。

公开(公告)号：US5963470A

公开(公告)日：1999-10-05

申请号：US019560

申请日：1998-02-06

申请人： Hirotoshi Sato

发明人： Hirotoshi Sato

IPC分类号： G11C11/412 ,  G11C11/00

CPC分类号： G11C11/412

摘要： In a SRAM cell including a bipolar transistor and a cut transistor, the threshold Vtheff (Driver) of driver transistor and the threshold Vtheff (Cut) of cut transistor are set such that they satisfy the expressions,Vtheff(Driver).gtoreq.�{log(1 .mu.A)}-{log(Vcc/10R)}!.times.S(1)�{log(1 .mu.A)}-{log((Ie.times.(1/(hFE+1)))/10)}!.times.S.ltoreq.Vtheff(Cut).ltoreq.�{log(1 .mu.A)}-{log(Vcc/R)}!.times.S(2)Vtheff(Cut)-S.ltoreq.Vtheff(Ac) (3)

摘要翻译： 在包括双极晶体管和截止晶体管的SRAM单元中，驱动晶体管的阈值Vtheff（驱动器）和切割晶体管的阈值Vtheff（Cut）被设置为使得它们满足表达式Vtheff（Driver）> / = [{ log（1μA）} - {log（Vcc / 10R）}] xS（1）[{log（1μA）} - {log（（Iex（1 /（hFE + 1）））/ 10）} ] xS（2）Vtheff（Cut）-S

公开(公告)号：US5754480A

公开(公告)日：1998-05-19

申请号：US597229

申请日：1996-02-06

申请人： Hirotoshi Sato

发明人： Hirotoshi Sato

IPC分类号： H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/0013 ,  H03K19/018571

摘要： When a potential D of an output node is drawn out to the level of ground potential GND by an n channel pull-down output transistor, a pull-down gate control transistor is rendered conductive. The output node and the n channel pull-down output transistor conduct.

摘要翻译： 当通过n沟道下拉输出晶体管将输出节点的电位D拉出到地电位GND的电平时，下拉栅极控制晶体管导通。 输出节点和n通道下拉输出晶体管导通。

公开(公告)号：US5734280A

公开(公告)日：1998-03-31

申请号：US683637

申请日：1996-07-15

申请人： Hirotoshi Sato

发明人： Hirotoshi Sato

IPC分类号： H03K17/22 ,  H03K23/40

CPC分类号： H03K17/223

摘要： A semiconductor integrated circuit device has an internal circuit node reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power. The internal circuit node reset generation circuit comprises an initial stage power on reset signal generation circuit, an initial stage signal transmission circuit for inputting a signal outputted by the initial stage power on reset signal generation circuit, a final stage power on reset signal generation circuit for inputting a signal outputted by the initial stage signal transmission circuit, and a final stage signal transmission circuit for inputting a signal outputted by the power on reset signal and outputting the output signal. When an operating source voltage lower limit value of the initial stage power on reset signal generation circuit is lower than that of the final stage signal transmission circuit and a source voltage has not reached a predetermined value, it is possible for the final stage power on reset signal generation circuit to generate an output signal without being influenced by the initial stage power on reset signal generation circuit, and to output an internal circuit inactivation signal for a certain time after application of power, and an inversion signal after passing the certain time. As a result, a certain internal circuit initialization time may be exactly established.

摘要翻译： 半导体集成电路器件具有内部电路节点复位信号产生电路，用于在施加电源之后立即以预定的时间延迟来反相输出信号。 内部电路节点复位生成电路包括初级上电复位信号生成电路，初始级信号发送电路，用于输入由复位​​信号生成电路的初始电源输出的信号，最终级上电复位信号生成电路， 输入由初始级信号发送电路输出的信号，以及最后级信号发送电路，用于输入由上电复位信号输出的信号并输出​​输出信号。 当初级上电复位信号发生电路的工作电源电压下限值低于最后级信号发送电路的工作源电压下限值，源电压未达到规定值时，最终级上电复位 信号发生电路，不受初始功率复位信号产生电路的影响而产生输出信号，并且在施加电力之后输出内部电路失活信号一定时间，以及经过一定时间之后的反相信号。 因此，可以精确地确定一定的内部电路初始化时间。

公开(公告)号：US20090196115A1

公开(公告)日：2009-08-06

申请号：US12360521

申请日：2009-01-27

申请人： Takeshi Agari ,  Hirotoshi Sato ,  Kiyoyasu Akai ,  Minoru Senda ,  Hiroaki Nakai

发明人： Takeshi Agari ,  Hirotoshi Sato ,  Kiyoyasu Akai ,  Minoru Senda ,  Hiroaki Nakai

IPC分类号： G11C5/14 ,  G11C8/08

CPC分类号： G11C5/14 ,  G11C5/148 ,  G11C8/08 ,  G11C8/10 ,  G11C11/417

摘要： When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

摘要翻译： 当操作模式转换到待机模式时，第一晶体管通过控制信号进入导通状态，并且字线由此被钳位到接地电压。 此外，第二晶体管进入非导通状态，并且切断向字线驱动器提供内部电源电压。 随后，停止内部电源电压的供应以节省电力。 当操作模式返回到正常模式时，内部电源电压的供应开始，随后通过控制信号使第一晶体管变为非导通状态，从而使第二晶体管进入导通状态 州。

公开(公告)号：US06294404B1

公开(公告)日：2001-09-25

申请号：US09568058

申请日：2000-05-10

申请人： Hirotoshi Sato

发明人： Hirotoshi Sato

IPC分类号： H01L2144

CPC分类号： G11C7/1072 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/2227 ,  Y10S438/90 ,  Y10S438/903 ,  Y10S438/91 ,  Y10T307/571 ,  Y10T307/615 ,  Y10T307/696

摘要： A semiconductor integrated circuit according to the present invention comprises a synchronous SRAM, a signal generation circuit generating a chip selection signal, a clock signal etc. supplied to the synchronous SRAM, a voltage set circuit setting the voltage of a system power supply line and a controller controlling the signal generation circuit and the voltage set circuit. When setting the synchronous SRAM in a power down mode, the chip selection signal is set in a nonselective state and the power supply voltage of the system power supply line is stepped down to a standby potential. Thus, the synchronous SRAM enters a standby state having extremely low power consumption.

摘要翻译： 根据本发明的半导体集成电路包括同步SRAM，产生芯片选择信号的信号发生电路，提供给同步SRAM的时钟信号等，设定系统电源线的电压的电压设定电路和 控制器控制信号发生电路和电压设定电路。 当在断电模式下设置同步SRAM时，芯片选择信号被设置为非选择状态，并且将系统电源线的电源电压降低到待机电位。 因此，同步SRAM进入具有极低功耗的待机状态。

公开(公告)号：US6118154A

公开(公告)日：2000-09-12

申请号：US947345

申请日：1997-10-08

申请人： Yasuo Yamaguchi ,  Hirotoshi Sato ,  Yasuo Inoue ,  Toshiaki Iwamatsu

发明人： Yasuo Yamaguchi ,  Hirotoshi Sato ,  Yasuo Inoue ,  Toshiaki Iwamatsu

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/786 ,  H01L23/60

CPC分类号： H01L27/0251

摘要： An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

摘要翻译： I / O保护电路包括连接在输入端和电源线之间的P沟道MOS晶体管和连接在输入端和接地线之间的N沟道MOS晶体管。 两个晶体管的栅极电极浮起来。 晶体管可以被栅极二极管代替。 此外，栅电极可以由与用于场屏蔽的栅电极相同的层形成。

公开(公告)号：US5841961A

公开(公告)日：1998-11-24

申请号：US487214

申请日：1995-06-07

申请人： Kunihiko Kozaru ,  Tomohisa Wada ,  Hirotoshi Sato

发明人： Kunihiko Kozaru ,  Tomohisa Wada ,  Hirotoshi Sato

IPC分类号： G06F12/08 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00 ,  G06F11/16

CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/848

摘要： In repairing a defective memory cell of a data memory placed in a data memory region, a repairing circuit which employs a repairing method causing some access penalty but having high repairing efficiency is located in a redundant row region and a redundant column region in the data memory region. On the other hand, in repairing a defective memory cell of a tag memory placed in a tag memory region, a repairing circuit which employs a repairing method having low repairing efficiency but causing little access penalty is located in a redundant column region in the tag memory region. Accordingly, optimal repair of a defective memory cell can be achieved according to respective functions of the tag memory and the data memory.

摘要翻译： 在修复放置在数据存储器区域中的数据存储器的有缺陷的存储单元的情况下，采用修复方法引起一些访问损失但具有高修复效率的修复电路位于数据存储器中的冗余行区域和冗余列区域中 地区。 另一方面，在修复放置在标签存储区域中的标签存储器的有缺陷的存储单元的情况下，使用维修效率低但导致小的访问损失的修复方法的修复电路位于标签存储器的冗余列区域中 地区。 因此，可以根据标签存储器和数据存储器的各自的功能来实现对缺陷存储单元的最佳修复。