公开(公告)号：US20120018807A1

公开(公告)日：2012-01-26

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  B82Y99/00

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US07511558B2

公开(公告)日：2009-03-31

申请号：US11362172

申请日：2006-02-27

申请人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

发明人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

IPC分类号： H03K3/01

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78648 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018585

摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。 在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。 或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。

公开(公告)号：US20070266933A1

公开(公告)日：2007-11-22

申请号：US11802048

申请日：2007-05-18

申请人： Ryuta Tsuchiya ,  Yoshinobu Kimura ,  Yusuke Morita

发明人： Ryuta Tsuchiya ,  Yoshinobu Kimura ,  Yusuke Morita

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B23/00 ,  C30B25/00

摘要： It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip. The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.

摘要翻译： 本发明的目的是提供一种以低成本和高产率制造SOI晶片的方法。 本发明的另一个目的是提供一种半导体器件，其还包括用作高电压区域的体型型MISFET及其制造方法，而不需要使用复杂的工艺并增加半导体芯片的尺寸。 制造半导体器件的方法包括选择性地外延生长单晶Si层并连续进行外延生长，而不会使基板温度在生长至室温期间增加甚至一次。 然后将外延生长的表面蚀刻并平坦化。 然后将衬底温度冷却至室温。

公开(公告)号：US07049589B2

公开(公告)日：2006-05-23

申请号：US10752527

申请日：2004-01-08

申请人： Atsuko Yamaguchi ,  Hiroshi Fukuda ,  Ryuta Tsuchiya ,  Hiroki Kawada ,  Shozo Yoneda

发明人： Atsuko Yamaguchi ,  Hiroshi Fukuda ,  Ryuta Tsuchiya ,  Hiroki Kawada ,  Shozo Yoneda

IPC分类号： G01N23/00

CPC分类号： G01B15/04 ,  G01B15/08

摘要： The present invention may include a pattern inspection method of extracting a pattern edge shape from an image obtained by a scanning microscope and inspecting the pattern. A control section and a computer of the scanning microscope process the intensity distribution of reflected electrons or secondary electrons, find the distribution of gate lengths in a single gate from data about edge positions, estimate the transistor performance by assuming a finally fabricated transistor to be a parallel connection of a plurality of transistors having various gate lengths, and determine the pattern quality and grade based on an estimated result. In this manner, it is possible to highly, accurately and quickly estimate an effect of edge roughness on the device performance and highly accurately and efficiently inspect patterns in accordance with device specifications.

摘要翻译： 本发明可以包括从由扫描显微镜获得的图像中提取图案边缘形状并检查图案的图案检查方法。 扫描显微镜的控制部分和计算机处理反射电子或二次电子的强度分布，从关于边缘位置的数据中找到单个栅极中栅极长度的分布，通过假设最终制造的晶体管为 具有各种栅极长度的多个晶体管的并联连接，并且基于估计结果确定图案质量和等级。 以这种方式，可以高度，准确和快速地估计边缘粗糙度对器件性能的影响，并且根据器件规格高精度和有效地检查图案。

公开(公告)号：US08790948B2

公开(公告)日：2014-07-29

申请号：US13303227

申请日：2011-11-23

申请人： Keiji Watanabe ,  Toshiyuki Mine ,  Akio Shima ,  Tomoko Sekiguchi ,  Ryuta Tsuchiya

发明人： Keiji Watanabe ,  Toshiyuki Mine ,  Akio Shima ,  Tomoko Sekiguchi ,  Ryuta Tsuchiya

IPC分类号： H01L21/00

CPC分类号： H01L31/02168 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/055 ,  H01L31/075 ,  H01L31/1872 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。

公开(公告)号：US08643117B2

公开(公告)日：2014-02-04

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US08409936B2

公开(公告)日：2013-04-02

申请号：US13363268

申请日：2012-01-31

申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 一种器件及其制造方法，其中，器件包括单晶半导体衬底和通过薄的掩埋绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的SOI衬底 以相同的步骤形成SOI型MISFET和体型MISFET的良好扩散层区域，漏极区域，栅极绝缘膜和栅极电极。 本体型MISFET和SOI型MISFET形成在同一衬底上，从而通过制造SOI型MISFET和体型MISFET的制造步骤，可以减少电路板面积并简化工艺。

公开(公告)号：US08034696B2

公开(公告)日：2011-10-11

申请号：US11802048

申请日：2007-05-18

申请人： Ryuta Tsuchiya ,  Yoshinobu Kimura ,  Yusuke Morita

发明人： Ryuta Tsuchiya ,  Yoshinobu Kimura ,  Yusuke Morita

IPC分类号： H01L21/20

CPC分类号： C30B23/00 ,  C30B25/00

摘要： It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip.The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.

摘要翻译： 本发明的目的是提供一种以低成本和高产率制造SOI晶片的方法。 本发明的另一个目的是提供一种半导体器件，其还包括用作高电压区域的体型型MISFET及其制造方法，而不需要使用复杂的工艺并增加半导体芯片的尺寸。 制造半导体器件的方法包括选择性地外延生长单晶Si层并连续进行外延生长，而不会使基板温度在生长至室温期间增加甚至一次。 然后将外延生长的表面蚀刻并平坦化。 然后将衬底温度冷却至室温。

公开(公告)号：US20090057746A1

公开(公告)日：2009-03-05

申请号：US12187504

申请日：2008-08-07

申请人： Nobuyuki Sugll ,  Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Nobuyuki Sugll ,  Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/788 ,  H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/93

摘要： A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n+ type semiconductor region formed in the SOI layer located on both sides of the gate electrode. The MOS varactor, is configured so that capacitance formed by the SOI layer, gate dielectric, and gate electrode is varied by applying bias voltage to the supporting substrate (p type well) under the gate electrode.

摘要翻译： 提供了一种具有无源元件的半导体器件，其特征是即使在通过施加反向偏置电压制造之后也是可调节的。 在包括支撑衬底，BOX层和SOI层的SOI衬底的主表面上形成MOS变容二极管，其包括在SOI层的表面上形成的栅极电介质，形成在栅极电介质上的栅电极和 n +型半导体区域形成在位于栅电极两侧的SOI层中。 MOS变容二极管被配置为使得由SOI层，栅极电介质和栅电极形成的电容通过在栅电极下施加偏置电压到支撑衬底（p型阱）来改变。

公开(公告)号：US20050139867A1

公开(公告)日：2005-06-30

申请号：US10933338

申请日：2004-09-03

申请人： Shin-ichi Saito ,  Tadashi Arai ,  Digh Hisamoto ,  Ryuta Tsuchiya ,  Hiroshi Fukuda ,  Takahiro Onai

发明人： Shin-ichi Saito ,  Tadashi Arai ,  Digh Hisamoto ,  Ryuta Tsuchiya ,  Hiroshi Fukuda ,  Takahiro Onai

IPC分类号： H01L29/78 ,  H01L21/335 ,  H01L29/76 ,  H01L49/00

CPC分类号： H01L49/003

摘要： The Mott transistor capable of operating at a room temperature can be realized by using a self-organized nanoparticle array for the channel portion. The nanoparticle used in the present invention comprises metal and organic molecules, and the size thereof is extremely small, that is, about a few nm. Therefore, the charging energy is sufficiently larger than the thermal energy kBT=26 meV, and the transistor can operate at a room temperature. Also, since the nanoparticles with a diameter of a few nm are arranged in a self-organized manner and the Mott transition can be caused by the change of a number of electrons of the surface density of about 1012 cm−2, the transistor can operate by the gate voltage of about several V.

摘要翻译： 能够在室温下操作的莫特晶体管可以通过使用用于沟道部分的自组织纳米颗粒阵列来实现。 本发明中使用的纳米颗粒包含金属和有机分子，其尺寸非常小，即约几nm。 因此，充电能量足够大于热能k B = 26meV，并且晶体管可以在室温下工作。 此外，由于直径为几nm的纳米颗粒以自组织的方式排列，并且Mott转变可以由表面密度约为10〜12的电子数量的变化引起， cm 2，晶体管可以通过约几V的栅极电压工作。