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公开(公告)号：US08790948B2
公开(公告)日：2014-07-29
申请号：US13303227
申请日：2011-11-23
申请人： Keiji Watanabe , Toshiyuki Mine , Akio Shima , Tomoko Sekiguchi , Ryuta Tsuchiya
发明人： Keiji Watanabe , Toshiyuki Mine , Akio Shima , Tomoko Sekiguchi , Ryuta Tsuchiya
IPC分类号： H01L21/00
CPC分类号： H01L31/02168 , B82Y20/00 , H01L31/0352 , H01L31/035236 , H01L31/055 , H01L31/075 , H01L31/1872 , Y02E10/52 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.
摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。
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公开(公告)号：US20120318337A1
公开(公告)日：2012-12-20
申请号：US13521487
申请日：2012-02-17
IPC分类号： H01L31/076
CPC分类号： H01L31/075 , H01L31/022441 , H01L31/0504 , H01L31/0508 , H01L31/0512 , H01L31/1804 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In a conventional solar cell, it has been difficult to ensure a sufficient light absorption and simultaneously to prevent current loss due to the reduction of the moving distance of electrons and holes. As a means for solving this difficulty, a plurality of a p-i-n junctions are stacked through an insulating film and are connected in parallel with each other using through-electrodes. In this case, the through-electrodes and the p-i-n junctions are connected through the p-layer or the n-layer, thereby moving electrons and holes in opposite directions and generating output current. In addition, the i-layer is made thicker than the p-layer and the n-layer in each of the p-i-n junctions, thereby ensuring a sufficient light absorption and simultaneously preventing current loss.
摘要翻译： 在常规太阳能电池中，难以确保足够的光吸收并且同时防止由于电子和空穴的移动距离的减小导致的电流损耗。 作为解决这个困难的手段，通过绝缘膜层叠多个p-i-n结，并且使用贯通电极彼此并联连接。 在这种情况下，贯通电极和p-i-n结通过p层或n层连接，从而沿相反方向移动电子和空穴并产生输出电流。 此外，i层比p-i-n结中的每一个中的p层和n层厚，从而确保足够的光吸收并同时防止电流损耗。
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公开(公告)号：US20150053261A1
公开(公告)日：2015-02-26
申请号：US14239612
申请日：2011-08-29
IPC分类号： H01L31/0352 , H01L31/0328
CPC分类号： H01L31/035254 , B82Y20/00 , H01L31/0328 , H01L31/035227 , H01L31/0682 , H01L31/0687 , Y02E10/544 , Y02E10/547
摘要： A surface reflectivity of a solar cell is reduced by applying a nanopillar array including a plurality of nanopillars to the solar cell. Further, by constituting the nanopillars with a Si/SiGe superlattice and controlling a Ge composition ratio of a SiGe layer (2), excited electron and hole are spatially separated in different layers, thus increasing a carrier lifetime, and at the same time, an optical-electrical conversion efficiency is improved by a multi-exciton phenomenon due to a quantum confinement effect. In addition, by forming an intermediate band by thinning a Si layer (1) and the SiGe layer (2), a carrier extraction efficiency is improved.
摘要翻译： 通过将包括多个纳米柱的纳米柱阵列施加到太阳能电池来减小太阳能电池的表面反射率。 此外，通过用Si / SiGe超晶格构成纳米级并控制SiGe层（2）的Ge组成比，激发的电子和空穴在不同层中空间分离，从而增加载流子寿命，同时， 光电转换效率由于量子限制效应而被多激子现象所改善。 此外，通过使Si层（1）和SiGe层（2）变薄来形成中间带，提高了载流子提取效率。
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公开(公告)号：US20140166100A1
公开(公告)日：2014-06-19
申请号：US14119195
申请日：2011-05-25
IPC分类号： H01L31/0352
CPC分类号： H01L31/035281 , H01L31/02366 , H01L31/03529 , Y02E10/50
摘要： A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.
摘要翻译： 包括基板1，具有与基板1连接的直径D1的纳米柱11和具有连接到基板1的直径D2的纳米柱12的太阳能电池的特征在于，D2大于D1，以实现太阳能电池， 作为表面结构，可以防止在太阳光的宽波长范围内的反射的纳米柱阵列结构。 由具有不同直径的两种类型的纳米柱形成的纳米柱阵列结构21具有由具有直径为D1的纳米柱11形成的纳米柱阵列结构的最小反射率点和由纳米柱12形成的纳米柱阵列结构的最小反射率点， 因此，能够防止太阳光的宽波长范围内的反射。
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公开(公告)号：US09257583B2
公开(公告)日：2016-02-09
申请号：US14119195
申请日：2011-05-25
IPC分类号： H01L31/00 , H01L31/0352 , H01L31/0236
CPC分类号： H01L31/035281 , H01L31/02366 , H01L31/03529 , Y02E10/50
摘要： A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.
摘要翻译： 包括基板1，具有与基板1连接的直径D1的纳米柱11和具有连接到基板1的直径D2的纳米柱12的太阳能电池的特征在于，D2大于D1，以实现太阳能电池， 作为表面结构，可以防止在太阳光的宽波长范围内的反射的纳米柱阵列结构。 由具有不同直径的两种类型的纳米柱形成的纳米柱阵列结构21具有由具有直径D1的纳米柱11形成的纳米柱阵列结构的最小反射率点和由纳米柱12形成的纳米柱阵列结构的最小反射率点， 因此，能够防止太阳光的宽波长范围内的反射。
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公开(公告)号：US09287292B2
公开(公告)日：2016-03-15
申请号：US12277833
申请日：2008-11-25
申请人： Ryuta Tsuchiya , Toshiaki Iwamatsu
发明人： Ryuta Tsuchiya , Toshiaki Iwamatsu
IPC分类号： H01L21/70 , H01L27/12 , H01L21/84 , H01L27/11 , H01L21/8238 , H01L27/105
CPC分类号： H01L27/1203 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/0649 , H03K17/6872
摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.
摘要翻译： 提供一种具有薄膜BOX-SOI结构并能够实现逻辑电路的高速操作和存储电路的稳定操作的半导体器件。 根据本发明的半导体器件包括半导体支撑衬底，厚度为10nm的绝缘层和半导体层。 在半导体层的上表面中，形成包括第一栅电极并构成逻辑电路的第一场效晶体管。 此外，在半导体层的上表面中，形成包括第二栅电极并构成存储电路的第二场效应晶体管。 在半导体支撑基板中形成具有不同导电类型的至少三个阱区。 在存在阱区的情况下，第一栅电极下方的半导体支撑衬底的区域和第二栅电极下方的半导体支撑衬底的区域彼此电分离。
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公开(公告)号：US07812398B2
公开(公告)日：2010-10-12
申请号：US12400324
申请日：2009-03-09
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/7846 , H01L29/785
摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。
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公开(公告)号：US20100084709A1
公开(公告)日：2010-04-08
申请号：US11993862
申请日：2006-06-30
申请人： Ryuta Tsuchiya , Shinichiro Kimura
发明人： Ryuta Tsuchiya , Shinichiro Kimura
IPC分类号： H01L29/786 , H01L21/336 , H01L21/86
CPC分类号： H01L27/12 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1207
摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.
摘要翻译： 当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。 另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。 使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜 并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。 由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。 可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。
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公开(公告)号：US20080258218A1
公开(公告)日：2008-10-23
申请号：US12105226
申请日：2008-04-17
IPC分类号： H01L27/01
CPC分类号： H01L29/045 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.
摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。
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公开(公告)号：US07385436B2
公开(公告)日：2008-06-10
申请号：US11714844
申请日：2007-03-07
申请人： Kiyoo Itoh , Ryuta Tsuchiya , Takayuki Kawahara
发明人： Kiyoo Itoh , Ryuta Tsuchiya , Takayuki Kawahara
IPC分类号： H03K3/01
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78648 , H03K19/0027 , H03K19/00384 , H03K19/018585
摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.
摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。 在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。 或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。
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