公开(公告)号：US20180232310A1

公开(公告)日：2018-08-16

申请号：US15587286

申请日：2017-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0817 ,  G06F12/0864

CPC classification number: G06F12/0822 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0864 ,  G06F12/0895 ,  G06F17/3033 ,  G06F2212/28 ,  G06F2212/62

Abstract: According to one embodiment, the method includes: providing a hybrid memory module including a DRAM cache, a flash memory, and an SRAM for storing a metadata cache; obtaining a host address by decoding a data access request received from a host computer, wherein the host address includes a DRAM cache tag and a DRAM cache index; obtaining a metadata address from the DRAM cache index, wherein the metadata address includes a metadata cache tag and a metadata cache index; determining a metadata cache hit based on a presence of a matching metadata cache entry in the metadata cache of the SRAM; in a case of the metadata cache hit, obtaining the data from the DRAM cache and skipping an access to the metadata of the DRAM cache; and returning the data obtained from the DRAM cache to the host computer.

公开(公告)号：US10049717B2

公开(公告)日：2018-08-14

申请号：US15169590

申请日：2016-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Kyung-Chang Ryoo

IPC: G06F12/00 ,  G11C11/406 ,  G06F12/02 ,  G11C14/00

Abstract: A method of wear leveling for a storage device or a memory device includes: receiving an inputted memory address; randomizing the inputted memory address to be a randomized memory address; and periodically reassigning the randomized memory address to be a different memory address.

公开(公告)号：US20180210843A1

公开(公告)日：2018-07-26

申请号：US15457813

申请日：2017-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/128 ,  G11C11/406

CPC classification number: G06F12/128 ,  G06F12/126 ,  G06F2212/1021 ,  G11C11/40618

Abstract: A method for replacing data on a volatile memory cache is provided. The volatile memory cache includes one or more memory banks and each of the memory banks includes a plurality of memory lines. The method includes: identifying a replacement ID for at least one of the memory lines to be replaced; identifying a refresh bank ID for one of the memory banks to be refreshed; determining whether or not a conflict exists between the replacement ID and the refresh bank ID; and selecting a new replacement ID if the conflict exists.

公开(公告)号：US20170357604A1

公开(公告)日：2017-12-14

申请号：US15285423

申请日：2016-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Young Lim ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Indong Kim

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G11C11/4094 ,  G06F12/0879 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/0891

Abstract: A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

公开(公告)号：US09837135B2

公开(公告)日：2017-12-05

申请号：US15227911

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G11C8/00 ,  G11C8/08 ,  G11C13/00

CPC classification number: G11C8/08 ,  G11C7/1018 ,  G11C8/04 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

公开(公告)号：US20170255418A1

公开(公告)日：2017-09-07

申请号：US15169609

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Craig Hanson ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies

公开(公告)号：US20250147659A1

公开(公告)日：2025-05-08

申请号：US19016833

申请日：2025-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Prasun Gera ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F9/30 ,  G06F15/78

Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.

公开(公告)号：US12181987B2

公开(公告)日：2024-12-31

申请号：US17499852

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Krishna Malladi ,  Hongzhong Zheng

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/20

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

公开(公告)号：US12032497B2

公开(公告)日：2024-07-09

申请号：US17469769

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng ,  Dimin Niu ,  Peng Gu

IPC: G06F13/16 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F13/1652 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F13/1694

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

公开(公告)号：US20230041850A1

公开(公告)日：2023-02-09

申请号：US17967733

申请日：2022-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit,a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.