公开(公告)号：US20240105267A1

公开(公告)日：2024-03-28

申请号：US18201331

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inho Kang ,  Daeseok Byeon ,  Beakhyung Cho ,  Min-Hwi Kim ,  Yongsung Cho ,  Gyosoo Choo

IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00

CPC classification number: G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

公开(公告)号：US20240055055A1

公开(公告)日：2024-02-15

申请号：US18197258

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Insu Kim ,  Jaehue Shin

IPC: G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  H01L25/0657 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

公开(公告)号：US20240036626A1

公开(公告)日：2024-02-01

申请号：US18137665

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunseok Nam ,  Seongmun Park ,  Yongsung Cho

IPC: G06F1/3203

CPC classification number: G06F1/3203

Abstract: An operating method of a power management integrated circuit includes outputting a first enable signal of a first regulator at a high level, determining whether a detection signal of a second regulator has a high level when a second enable signal of the second regulator has a low level, changing set values of the first regulator and the second regulator for a parallel mode when the detection signal has a high level, setting the first regulator and the second regulator to the changed set values, and outputting the second enable signal at a high level.

公开(公告)号：US11646064B2

公开(公告)日：2023-05-09

申请号：US17207398

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US20230131700A1

公开(公告)日：2023-04-27

申请号：US18085963

申请日：2022-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C16/34

Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

公开(公告)号：US11626166B2

公开(公告)日：2023-04-11

申请号：US17229053

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  H01L27/11582

Abstract: A memory device for performing temperature compensation and an operating method thereof are provided. The memory device includes a memory cell array; a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a page buffer connected to each of the plurality of bit lines, and configured to perform a pre-charge operation during a pre-charge period for data reading; and a control logic configured to differently control the pre-charge operation of the page buffer circuit according to a detected temperature, wherein the pre-charge period includes a first period in which the plurality of bit lines are overdriven and a second period in which the plurality of bit lines are driven at a voltage lower than that of the first period, and the first period where the detected temperature is a first temperature is set to be shorter than the second period where the detected temperature is a second temperature higher than the first temperature.

公开(公告)号：US20220020404A1

公开(公告)日：2022-01-20

申请号：US17207398

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US10269438B2

公开(公告)日：2019-04-23

申请号：US15701801

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung Cho

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/28 ,  G11C16/08 ,  G11C16/34

Abstract: A nonvolatile memory device includes a first cell string including a first dummy cell and connected to a selected string select line, a second cell string including a second dummy cell and connected to the selected string select line, a page buffer circuit configured to select one of the first and second cell strings to read data in a read operation, and a control logic circuit configured to apply a first bit line voltage to a bit line connected to the selected one of the first and second cell strings and a second bit line voltage to a bit line connected to an unselected one of the first and second cell strings in the read operation. The control logic circuit turns off the second dummy cell when the first cell string is selected and turns off the first dummy cell when the second cell string is selected.