公开(公告)号：US10546875B2

公开(公告)日：2020-01-28

申请号：US15996483

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Pansuk Kwak ,  Chaehoon Kim ,  Hongsoo Jeon ,  Jeunghwan Park ,  Bongsoon Lim

IPC: H01L27/11 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  H01L27/1157 ,  G11C16/08

Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.

公开(公告)号：US20230223056A1

公开(公告)日：2023-07-13

申请号：US18125260

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C16/24 ,  H10B80/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  H10B80/00 ,  G11C16/0483

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US09685211B2

公开(公告)日：2017-06-20

申请号：US15018180

申请日：2016-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeunghwan Park ,  Sunghoon Kim

IPC: G11C5/06 ,  G11C7/18 ,  G11C16/26 ,  H01L27/02 ,  G11C5/02 ,  G11C7/10 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: G11C7/18 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C16/26 ,  H01L27/0207 ,  H01L27/11573 ,  H01L27/11582

Abstract: The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.

公开(公告)号：US11646064B2

公开(公告)日：2023-05-09

申请号：US17207398

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US20220020404A1

公开(公告)日：2022-01-20

申请号：US17207398

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US11974440B2

公开(公告)日：2024-04-30

申请号：US17219299

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung Cho ,  Inho Kang ,  Ansoo Park ,  Jeunghwan Park ,  Dongha Shin ,  Jeawon Jeong

IPC: G11C11/00 ,  G06F3/06 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/40 ,  G06F3/0656 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.

公开(公告)号：US11842790B2

公开(公告)日：2023-12-12

申请号：US18125260

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US20160276001A1

公开(公告)日：2016-09-22

申请号：US15018180

申请日：2016-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeunghwan Park ,  Sunghoon KIM

IPC: G11C7/10 ,  G11C7/18

CPC classification number: G11C7/18 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C16/26 ,  H01L27/0207 ,  H01L27/11573 ,  H01L27/11582

Abstract: The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.

Abstract translation: 本发明构思涉及非易失性存储器件。 非易失性存储器件可以包括存储单元阵列和通过位线连接到存储单元阵列的页缓冲器电路。 页面缓冲电路可以包括衬底，衬底上的位线选择晶体管，并且连接到相应的位线，以及通过线连接到位线选择晶体管的衬底上的锁存器。 线可以在衬底的顶表面上方并平行的第一平面上，并且可以通过第一接触连接到位线选择晶体管中的相应位置。 位线可以在衬底的上表面上方并且平行于第二平面，并且可以通过第二触点连接到相应的位线选择晶体管。