公开(公告)号：US20230253353A1

公开(公告)日：2023-08-10

申请号：US17667238

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L25/0657 ,  H01L25/0652 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/32 ,  H01L24/29 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/80895 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/29575 ,  H01L2224/29687 ,  H01L2224/32145 ,  H01L2224/0801 ,  H01L2224/08147 ,  H01L2224/06131 ,  H01L2224/0603 ,  H01L2224/05007 ,  H01L2224/05073 ,  H01L2224/05565 ,  H01L2224/05573 ,  H01L2224/0903 ,  H01L2224/0913

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

公开(公告)号：US20230044232A1

公开(公告)日：2023-02-09

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Yuki MIZUTANI ,  Hisakazu OTOI ,  Masaaki HIGASHITANI ,  Hiroyuki OAGAWA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/48 ,  G11C8/14

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20220399362A1

公开(公告)日：2022-12-15

申请号：US17347810

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki MIZUTANI ,  Fumiaki TOYAMA ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528

Abstract: A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.

公开(公告)号：US20220399358A1

公开(公告)日：2022-12-15

申请号：US17498100

申请日：2021-10-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki MIZUTANI ,  Fumiaki TOYAMA ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00

Abstract: A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.

公开(公告)号：US20220367499A1

公开(公告)日：2022-11-17

申请号：US17317578

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20210320075A1

公开(公告)日：2021-10-14

申请号：US17357040

申请日：2021-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI ,  Ramy Nashed Bassely SAID

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first metallic plates. First bonding pads including a respective one of the first metallic plates are formed. A first polymer material layer can be formed over the first bonding pads. A second semiconductor die including second bonding pads is bonded to the first bonding pads to form a bonded assembly.

公开(公告)号：US20210217716A1

公开(公告)日：2021-07-15

申请号：US16742213

申请日：2020-01-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11526 ,  H01L25/00

Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

公开(公告)号：US20210159216A1

公开(公告)日：2021-05-27

申请号：US16694438

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L25/00 ,  H01L27/06

Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.

公开(公告)号：US20200343161A1

公开(公告)日：2020-10-29

申请号：US16391632

申请日：2019-04-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/18 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.

公开(公告)号：US20200066703A1

公开(公告)日：2020-02-27

申请号：US16669888

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Masaaki HIGASHITANI ,  Fumiaki TOYAMA ,  Akio NISHIDA

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00 ,  H01L27/11575 ,  H01L27/1157

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.