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    ELECTRONIC DEVICE
    31.
    发明申请
    ELECTRONIC DEVICE 有权
    电子设备

    公开(公告)号：US20160261272A1

    公开(公告)日：2016-09-08

    申请号：US15050699

    申请日：2016-02-23

    Applicant: Semiconductor Energy Laboratory Co., LTD.

    Inventor： Takayuki IKEDA ,  Munehiro KOZUMA ,  Takeshi AOKI

    IPC: H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/17724 ,  H03K19/0008 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/17776

    Abstract: A novel electronic device including a reconfigurable circuit is provided. In the electronic device including a reconfigurable circuit capable of executing multi-context operation, a context selection signal is locally generated. For example, a context selection signal is generated in the reconfigurable circuit with the use of context determination data contained in an output of another logic block, for example. The range of application of the context selection signal can be set as appropriate by a user. Thus, multi-context operation performed locally and partly enables efficient use of the circuit. Memory usage can be reduced and its efficiency can be improved compared to the case of using global multi-context driving. Other embodiments may be disclosed and claimed.

    Abstract translation: 提供了一种包括可重构电路的新型电子设备。 在包括能够执行多上下文操作的可重构电路的电子设备中，本地生成上下文选择信号。 例如，例如，通过使用包含在另一逻辑块的输出中的上下文确定数据，在可重构电路中生成上下文选择信号。 上下文选择信号的应用范围可以由用户适当地设定。 因此，本地执行的多上下文操作部分地实现了电路的有效使用。 与使用全球多上下文驱动的情况相比，可以降低内存使用并提高其效率。 可以公开和要求保护其他实施例。

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    32.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20250088766A1

    公开(公告)日：2025-03-13

    申请号：US18910287

    申请日：2024-10-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takuro KANEMURA

    IPC: H04N25/74 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00 ,  H10K39/32

    Abstract: A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1−I2−I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    35.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20230132059A1

    公开(公告)日：2023-04-27

    申请号：US17915673

    申请日：2021-04-05

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takuro KANEMURA

    IPC: H10K39/32 ,  G06F7/523 ,  G06F7/50

    Abstract: A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug. Note that the first to fourth wirings are parallel to each other, and the distance between the third wiring and the fourth wiring is greater than or equal to 0.9 times and less than or equal to 1.1 times the distance between the first wiring and the second wiring.

    SEMICONDUCTOR DEVICE
    36.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230040508A1

    公开(公告)日：2023-02-09

    申请号：US17788050

    申请日：2020-12-14

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Masashi OOTA ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Shunpei YAMAZAKI

    IPC: H01L29/786 ,  G06N3/02 ,  H01L29/423 ,  H01L27/105

    Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

    OPERATION CIRCUIT, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
    37.
    发明申请
    OPERATION CIRCUIT, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20220374203A1

    公开(公告)日：2022-11-24

    申请号：US17769845

    申请日：2020-10-15

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Takuro KANEMURA

    IPC: G06F7/544

    Abstract: A semiconductor device that inhibits signal delay and can perform parallel product-sum operations is provided. The semiconductor device includes first to fourth registers, an adder, a multiplier, a selector, and a first memory unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and an output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, and an output terminal of the adder is electrically connected to an input terminal of the third register. An output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register, and the first memory unit is electrically connected to a second input terminal of the multiplier. The first memory unit has a function reading out first data corresponding to a context signal input to the first memory unit and inputting the first data to the second input terminal of the multiplier.

    SEMICONDUCTOR DEVICE
    38.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220276838A1

    公开(公告)日：2022-09-01

    申请号：US17716239

    申请日：2022-04-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro KOZUMA ,  Takeshi AOKI ,  Seiichi YONEDA ,  Yoshiyuki KUROKAWA

    IPC: G06F7/544 ,  G06N3/063

    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

    AI SYSTEM AND OPERATION METHOD OF AI SYSTEM
    40.
    发明申请
    AI SYSTEM AND OPERATION METHOD OF AI SYSTEM 有权

    公开(公告)号：US20220180159A1

    公开(公告)日：2022-06-09

    申请号：US17436467

    申请日：2020-01-24

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Hajime KIMURA ,  Rihito WADA ,  Masayuki KIMURA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI

    IPC: G06N3/063 ,  G06F16/93 ,  G06F30/327

    Abstract: A system that creates a net list from a circuit diagram or a document showing a circuit structure is provided. The system is an AI system including a first electronic device. The first electronic device includes an input/output interface, a control portion, and a first conversion portion. The input/output interface is electrically connected to the control portion, and the first conversion portion is electrically connected to the control portion. The input/output interface has a function of transmitting input data generated by a user's operation to the control portion, and the control portion has a function of transmitting the input data to the first conversion portion. Note that the input data is a circuit diagram illustrating a circuit structure or a document file showing the circuit structure. The first conversion portion includes a circuit where a neural network is formed, and the input data is converted to a net list with the use of the neural network of the first conversion portion.

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