公开(公告)号：US20170040457A1

公开(公告)日：2017-02-09

申请号：US15224958

申请日：2016-08-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Daisuke MATSUBAYASHI ,  Yuichi SATO

IPC: H01L29/786 ,  H01L29/45 ,  H01L21/441 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

Abstract translation: 提供其中寄生电容减小的半导体器件。 第一绝缘层沉积在衬底上。 在第一绝缘层上沉积第一氧化物绝缘层和氧化物半导体层。 第二氧化物绝缘层沉积在氧化物半导体层和第一绝缘层上。 在第二氧化物绝缘层上沉积第二绝缘层和第一导电层。 通过蚀刻形成栅极电极层，栅极绝缘层和第三氧化物绝缘层。 形成包括与栅电极层的侧面接触的区域的侧壁绝缘层。 在栅电极层，侧壁绝缘层，氧化物半导体层和第一绝缘层上沉积第二导电层。 在第二导电层上沉积第三导电层。 通过进行热处理，在氧化物半导体层中形成低电阻区域。 包含在第二导电层中的元素通过进行热处理从第二导电层移动到氧化物半导体层侧。 包含在氧化物半导体层中的元素通过进行热处理从氧化物半导体层移动到第三导电层侧。

公开(公告)号：US20160284864A1

公开(公告)日：2016-09-29

申请号：US15177447

申请日：2016-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC: H01L29/786 ,  H01L27/12 ,  G02F1/1362 ,  H01L29/66 ,  G02F1/1368 ,  H01L29/24 ,  H01L27/105

CPC classification number: H01L29/78618 ,  G02F1/136204 ,  G02F1/136213 ,  G02F1/136286 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/0259 ,  H01L21/265 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region. By providing a microvoid in the source region and the drain region formed in an oxide semiconductor film, hydrogen contained in the channel region of an oxide semiconductor film can be captured in the microvoid.

公开(公告)号：US20150037932A1

公开(公告)日：2015-02-05

申请号：US14459597

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

Abstract translation: 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

公开(公告)号：US20140209899A1

公开(公告)日：2014-07-31

申请号：US14227231

申请日：2014-03-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shinji OHNO ,  Yuichi SATO ,  Junichi KOEZUKA ,  Sachiaki TEZUKA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1225

Abstract: To provide an oxide semiconductor film including a low-resistance region, which can be applied to a transistor. To provide a transistor including the oxide semiconductor film, which can perform at high speed. To provide a high-performance semiconductor device including the transistor including the oxide semiconductor film, which can perform at high speed, with high yield. A film having a reducing property is formed over the oxide semiconductor film. Next, part of oxygen atoms are transferred from the oxide semiconductor film to the film having a reducing property. Next, an impurity is added to the oxide semiconductor film through the film having a reducing property and then, the film having a reducing property is removed, so that a low-resistance region is formed in the oxide semiconductor film.

Abstract translation: 提供一种可以应用于晶体管的包含低电阻区域的氧化物半导体膜。 提供可以高速执行的包括氧化物半导体膜的晶体管。 提供一种高性能半导体器件，其包括能够以高产率高速执行的包括氧化物半导体膜的晶体管。 在氧化物半导体膜上形成具有还原性的膜。 接下来，氧原子的一部分从氧化物半导体膜转移到具有还原性的膜。 接下来，通过具有还原性的膜向氧化物半导体膜添加杂质，然后去除具有还原性的膜，从而在氧化物半导体膜中形成低电阻区域。