-
31.发明授权公开(公告)号：US09640230B2
公开(公告)日：2017-05-02
申请号：US14938304
申请日：2015-11-11
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Marco Pasotti , Fabio De Santis
CPC classification number: G11C7/22 , G11C7/06 , G11C7/062 , G11C7/08 , G11C7/10 , G11C16/0441 , G11C16/28
Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
-
32.发明申请IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY 有权识别非易失性存储器中存储器细胞的一个条件的条件公开(公告)号：US20160064046A1
公开(公告)日：2016-03-03
申请号：US14938304
申请日：2015-11-11
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Marcella Carissimi , Marco Pasotti , Fabio De Santis
IPC: G11C7/06
CPC classification number: G11C7/22 , G11C7/06 , G11C7/062 , G11C7/08 , G11C7/10 , G11C16/0441 , G11C16/28
Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
Abstract translation: 互补型的非易失性存储器包括存储器单元的扇区，每个单元由直接存储单元和互补存储单元形成。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 选择扇区，并且确定处于编程状态的多个存储单元和被擦除状态的多个存储单元。 根据该信息，通过编程状态下的存储单元的数量和被擦除状态的存储单元的数量之间的比较来识别所选扇区的状态。
-
公开(公告)号：US12211582B2
公开(公告)日：2025-01-28
申请号：US17718755
申请日：2022-04-12
Inventor： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.
-
公开(公告)号：US12046987B2
公开(公告)日：2024-07-23
申请号：US17582431
申请日：2022-01-24
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla , Marcella Carissimi
CPC classification number: H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
-
公开(公告)号：US11894052B2
公开(公告)日：2024-02-06
申请号：US17718908
申请日：2022-04-12
Inventor： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico , Paolo Romele
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/0026 , G11C13/0038
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
-
Patent Agency Ranking
公开(公告)号：US11615820B1
公开(公告)日：2023-03-28
申请号：US17490976
申请日：2021-09-30
Inventor： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
-
公开(公告)号：US10755777B2
公开(公告)日：2020-08-25
申请号：US16169763
申请日：2018-10-24
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Marco Pasotti , Chantal Auricchio
Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.
-
公开(公告)号：US10068643B2
公开(公告)日：2018-09-04
申请号：US15422290
申请日：2017-02-01
Inventor： Marco Pasotti , Marcella Carissimi , Rajat Kulshrestha , Chantal Auricchio
Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.
-
公开(公告)号：US10049736B2
公开(公告)日：2018-08-14
申请号：US15433795
申请日：2017-02-15
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
-
公开(公告)号：US20180107612A1
公开(公告)日：2018-04-19
申请号：US15297897
申请日：2016-10-19
Applicant: STMicroelectronics S.r.l
Inventor： Emanuela Calvetti , Marcella Carissimi
IPC: G06F13/16 , G06F13/364 , G06F13/42
CPC classification number: G06F13/161 , G06F13/1689 , G06F13/364 , G06F13/4291
Abstract: An embodiment method includes storing, in each of a first plurality of memory locations of a memory, an address of another of the first plurality of memory locations, and reading, from a bus signal received at the memory, an address of a first one of the first plurality of memory locations. The method further includes reading data stored in the first one of the first plurality of memory locations, and determining, using the read data, whether a read error has occurred.
-
-
-
-
-
-
-
-
-
Search Results
43
records
(took 0.022 seconds)
