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公开(公告)号：US11798630B2
公开(公告)日：2023-10-24
申请号：US17407903
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Fabio Enrico Carlo Disegni , Chantal Auricchio , Cesare Torti , Davide Manfre' , Laura Capecchi , Emanuela Calvetti , Stefano Zanchi
CPC classification number: G11C16/102 , G11C7/04 , G11C16/24 , G11C16/28 , G11C16/30
Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
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32.发明授权公开(公告)号：US11756614B2
公开(公告)日：2023-09-12
申请号：US17657861
申请日：2022-04-04
Applicant: STMicroelectronics S.r.l.
CPC classification number: G11C13/0004 , G11C7/02 , G11C7/06 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0069
Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US11557340B2
公开(公告)日：2023-01-17
申请号：US17410141
申请日：2021-08-24
Applicant: STMicroelectronics S.r.l.
Inventor： Michele La Placa , Fabio Enrico Carlo Disegni , Federico Goller
Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.
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34.发明授权公开(公告)号：US11328768B2
公开(公告)日：2022-05-10
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US11133064B2
公开(公告)日：2021-09-28
申请号：US16931335
申请日：2020-07-16
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Laura Capecchi , Marco Pasotti , Fabio Enrico Carlo Disegni
Abstract: A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.
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Patent Agency Ranking
公开(公告)号：US11049561B2
公开(公告)日：2021-06-29
申请号：US16903264
申请日：2020-06-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Federico Goller , Cesare Torti , Marcella Carissimi , Emanuela Calvetti
Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.
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37.发明申请公开(公告)号：US20210193220A1
公开(公告)日：2021-06-24
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US20210012836A1
公开(公告)日：2021-01-14
申请号：US16924760
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Michele La Placa , Fabio Enrico Carlo Disegni , Federico Goller
Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.
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39.发明授权公开(公告)号：US10811093B2
公开(公告)日：2020-10-20
申请号：US16225492
申请日：2018-12-19
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni
Abstract: In an embodiment, a method of accessing logic data stored in a differential memory using single-ended mode includes: storing second logic data in an auxiliary memory module of the differential memory by copying first logic data stored in a first main memory module of the differential memory into the auxiliary memory module; refreshing the first logic data; receiving a request for reading the first logic data; when refreshing the first logic data, fetching the second logic data when refreshing the first logic data in response to the request for reading the first logic data; and when not refreshing the first logic data, fetching the first logic data in response to the request for reading the first logic data.
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公开(公告)号：US20180240519A1
公开(公告)日：2018-08-23
申请号：US15797732
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Manfre , Cesare Torti , Fabio Enrico Carlo Disegni
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C8/16 , G11C13/0004 , G11C13/0023
Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
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