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    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
    31.
    发明公开
    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT 审中-公开

    公开(公告)号：US20240105268A1

    公开(公告)日：2024-03-28

    申请号：US18529897

    申请日：2023-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

    IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

    CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

    Abstract: A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    NON-VOLATILE MEMORY DEVICE
    34.
    发明公开
    NON-VOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20230267975A1

    公开(公告)日：2023-08-24

    申请号：US18104533

    申请日：2023-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungyeon Kim ,  Daeseok Byeon

    IPC: G11C7/10 ,  G11C5/06

    CPC classification number: G11C7/1039 ,  G11C7/1069 ,  G11C5/063

    Abstract: A non-volatile memory device includes a first semiconductor layer including a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, wherein the first memory cell array and the second memory cell array each include a plurality of word lines, a plurality of memory cells, and a plurality of bit lines, and a second semiconductor layer including a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, wherein the page buffer circuit region overlaps a boundary region between the first cell region and the second cell region when viewed from the vertical direction.

    Semiconductor device
    37.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11637077B2

    公开(公告)日：2023-04-25

    申请号：US17218230

    申请日：2021-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

    IPC: H01L21/00 ,  H01L23/60 ,  H01L23/528 ,  H01L27/092

    Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

    Memory device, memory system and autonomous driving apparatus
    38.
    发明授权
    Memory device, memory system and autonomous driving apparatus 有权

    公开(公告)号：US11513730B2

    公开(公告)日：2022-11-29

    申请号：US16892574

    申请日：2020-06-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

    IPC: G06F11/00 ,  G06F3/06 ,  G05D1/00 ,  G06F13/16 ,  G11C5/02 ,  B60W50/00

    Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

    Memory device including pass transistor circuit
    39.
    发明授权
    Memory device including pass transistor circuit 有权

    公开(公告)号：US11462275B2

    公开(公告)日：2022-10-04

    申请号：US17227501

    申请日：2021-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

    IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    Memory device
    40.
    发明授权
    Memory device 有权

    公开(公告)号：US11456317B2

    公开(公告)日：2022-09-27

    申请号：US17023053

    申请日：2020-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

    IPC: H01L27/11573 ,  H01L27/11582 ,  G11C8/14 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

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