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    Semiconductor memory device
    32.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11696434B2

    公开(公告)日：2023-07-04

    申请号：US17241860

    申请日：2021-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Kyunghwan Lee ,  Dongoh Kim ,  Yongseok Kim ,  Hui-Jung Kim ,  Min Hee Cho

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/395 ,  H10B12/50

    Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

    Sensing module and electronic device including the same
    33.
    发明授权
    Sensing module and electronic device including the same 有权

    公开(公告)号：US11675112B2

    公开(公告)日：2023-06-13

    申请号：US16806011

    申请日：2020-03-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Daekwan Kim ,  Yohwan Noh

    IPC: G02B3/00 ,  G06V40/13 ,  G06V10/10 ,  G06V40/12

    CPC classification number: G02B3/0062 ,  G06V10/17 ,  G06V40/1318 ,  G06V40/1324 ,  G06V40/1341

    Abstract: An electronic device includes a substrate, a plurality of light sources, the plurality of light sources configured to emit an optical signal to an object through the substrate, at least one sensor underneath the substrate, the at least one sensor configured to detect biometric information associated with the object by receiving a reflected light signal, the reflected light signal corresponding to the optical signal reflected off the object and transferred through the substrate, and a multi-lens array including at least one support layer, a plurality of first lenses, and a plurality of second lenses, the at least one support layer in an upper portion of the at least one sensor, the plurality of first lenses on an upper surface of the at least one support layer, and the plurality of second lenses on a lower surface of the at least one support layer.

    OPERATION METHOD OF USER EQUIPMENT USING CONNECTED MODE DISCONTINUOUS RECEPTION
    34.
    发明公开
    OPERATION METHOD OF USER EQUIPMENT USING CONNECTED MODE DISCONTINUOUS RECEPTION 审中-公开

    公开(公告)号：US20230156600A1

    公开(公告)日：2023-05-18

    申请号：US18054579

    申请日：2022-11-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inheon Kang ,  Kyunghwan Lee

    IPC: H04W52/02 ,  H04W24/10

    CPC classification number: H04W52/0232 ,  H04W24/10

    Abstract: The devices, systems, methods, and techniques described herein provide for efficient operation of a user equipment (UE) configured to support mobility mechanisms while using connected mode discontinuous reception (CDRX). In some aspects, a UE configured to use CDRX may measure objects according to a No DRX minimum measurement period (e.g., a minimum measurement period configured when no DRX is used). Because the No DRX minimum measurement period may be shorter than a DRX minimum measurement period, the UE may be able to measure objects more frequently and improve mobility performance. Further, although the UE may perform measurements according to the No DRX minimum measurement period, the UE may still report the measurements according to a DRX minimum measurement period. Thus, the UE may report measurements less frequently, and the UE may sleep during more off-durations of a CDRX cycle, resulting in reduced power consumption.

    Semiconductor devices including semiconductor pattern
    35.
    发明授权
    Semiconductor devices including semiconductor pattern 有权

    公开(公告)号：US11581316B2

    公开(公告)日：2023-02-14

    申请号：US17092593

    申请日：2020-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L27/102 ,  H01L29/74

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    Semiconductor memory device including variable resistance layer
    36.
    发明授权
    Semiconductor memory device including variable resistance layer 有权

    公开(公告)号：US11538859B2

    公开(公告)日：2022-12-27

    申请号：US16657453

    申请日：2019-10-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

    Resistive memory device controlling bitline voltage
    37.
    发明授权
    Resistive memory device controlling bitline voltage 有权

    公开(公告)号：US11430515B2

    公开(公告)日：2022-08-30

    申请号：US17036004

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Cheonan Lee ,  Satoru Yamada ,  Junhee Lim

    IPC: G11C13/00 ,  H01L27/24

    Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

    Vertical memory devices
    39.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11158651B2

    公开(公告)日：2021-10-26

    申请号：US16773103

    申请日：2020-01-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Kwangsoo Kim ,  Taehun Kim ,  Yongseok Kim ,  Kohji Kanamori

    IPC: H01L29/792 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/02

    Abstract: A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.

    Semiconductor device for preventing defects between bit lines and channels
    40.
    发明授权
    Semiconductor device for preventing defects between bit lines and channels 有权

    公开(公告)号：US11049847B2

    公开(公告)日：2021-06-29

    申请号：US16734505

    申请日：2020-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kohji Kanamori ,  Yongseok Kim ,  Kyunghwan Lee ,  Junhee Lim ,  Jeehoon Han

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor device includes a first semiconductor structure comprising a substrate and a circuit element, and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes a base layer, a first memory cell structure, a second memory cell structure, and common bit lines between the first memory cell structure and the second memory cell structure. The first memory cell structure includes first gate electrodes, first channel structures, and first string select channel structures. The second memory cell structure includes second gate electrodes, second channel structures, second string select channel structures, and connection regions between the second channel structures and the second string select channel structures. The first memory cell structure further includes first channel pads between the common bit lines and the first string select channel structures, and the second memory cell structure further includes second channel pads extending along the common bit lines.

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