公开(公告)号：US10256324B2

公开(公告)日：2019-04-09

申请号：US15664226

申请日：2017-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Changhee Kim ,  Yunil Lee ,  Mirco Cantoro ,  Junggun You ,  Donghun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

公开(公告)号：US09966377B2

公开(公告)日：2018-05-08

申请号：US15409202

申请日：2017-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  YeonCheol Heo

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/306 ,  H01L29/267 ,  H01L29/06 ,  H01L27/11 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.

公开(公告)号：US20170345927A1

公开(公告)日：2017-11-30

申请号：US15350686

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon-cheol HEO ,  Maria TOLEDANO LUQUE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/207 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7827 ,  H01L21/30612 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66666

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other

公开(公告)号：US09679975B2

公开(公告)日：2017-06-13

申请号：US14823229

申请日：2015-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L31/00 ,  H01L29/74 ,  H01L23/52 ,  H01L29/66 ,  H01L29/267 ,  H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.