公开(公告)号：US10396088B2

公开(公告)日：2019-08-27

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sunil Shim ,  Jaeduk Lee ,  Jaehoon Jang ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

公开(公告)号：US09401209B2

公开(公告)日：2016-07-26

申请号：US14826814

申请日：2015-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Jang-Gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

IPC: H01L29/78 ,  G11C16/04 ,  H01L23/535 ,  H01L27/115

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

公开(公告)号：US09330770B2

公开(公告)日：2016-05-03

申请号：US14590665

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US09117923B2

公开(公告)日：2015-08-25

申请号：US13830208

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmin Hwang ,  Wonseok Cho ,  Jinsoo Lim

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.

Abstract translation: 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，形成导电图案。

公开(公告)号：US08824209B2

公开(公告)日：2014-09-02

申请号：US13836212

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/66 ,  G11C16/10 ,  H01L29/788

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。

公开(公告)号：US08637920B2

公开(公告)日：2014-01-28

申请号：US13684857

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract translation: 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。