公开(公告)号：US20200051993A1

公开(公告)日：2020-02-13

申请号：US16142752

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US20200006364A1

公开(公告)日：2020-01-02

申请号：US16019961

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Jayavel PACHAMUTHU

IPC: H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US20230363161A1

公开(公告)日：2023-11-09

申请号：US18045070

申请日：2022-10-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical composite metal oxide semiconductor channel that contains an outer semiconducting metal oxide channel layer having a first band gap and an inner semiconducting metal oxide channel layer having a second band gap that is different from the first band gap.

公开(公告)号：US20230363158A1

公开(公告)日：2023-11-09

申请号：US17661783

申请日：2022-05-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical composite metal oxide semiconductor channel having a different composition between its inner and outer portions.

公开(公告)号：US20230253353A1

公开(公告)日：2023-08-10

申请号：US17667238

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L25/0657 ,  H01L25/0652 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/32 ,  H01L24/29 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/80895 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/29575 ,  H01L2224/29687 ,  H01L2224/32145 ,  H01L2224/0801 ,  H01L2224/08147 ,  H01L2224/06131 ,  H01L2224/0603 ,  H01L2224/05007 ,  H01L2224/05073 ,  H01L2224/05565 ,  H01L2224/05573 ,  H01L2224/0903 ,  H01L2224/0913

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

公开(公告)号：US20210408033A1

公开(公告)日：2021-12-30

申请号：US16912279

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar BARASKAR ,  Raghuveer S. MAKALA ,  Peter RABKIN

IPC: H01L27/11582 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/78

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US20210408032A1

公开(公告)日：2021-12-30

申请号：US16912196

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar BARASKAR ,  Raghuveer S. MAKALA ,  Peter RABKIN

IPC: H01L27/11582 ,  H01L21/762 ,  H01L27/11556 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US20210375910A1

公开(公告)日：2021-12-02

申请号：US16887818

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Peter RABKIN ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US20210375909A1

公开(公告)日：2021-12-02

申请号：US16887738

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Peter RABKIN ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/207 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US20210375908A1

公开(公告)日：2021-12-02

申请号：US16887659

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Peter RABKIN ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.