公开(公告)号：US06211082B1

公开(公告)日：2001-04-03

申请号：US09021462

申请日：1998-02-10

Applicant: Bong-young Yoo ,  Byung-Lyul Park ,  Dae-hong Ko ,  Sang-in Lee

Inventor： Bong-young Yoo ,  Byung-Lyul Park ,  Dae-hong Ko ,  Sang-in Lee

IPC: H01L2144

CPC classification number: C23C16/08 ,  H01L21/28568

Abstract: A tungsten or other metal layer is chemical vapor deposited using a source gas containing tungsten, a reducing gas and a nitrogen-containing gas. The nitrogen-containing gas can act as a surface roughness reducing gas that reduces the roughness of the tungsten layer compared to a tungsten layer that is chemical vapor deposited using the source gas containing tungsten and the reducing gas, but without using the surface roughness reducing gas. Viewed in another way, the nitrogen-containing gas acts as a growth rate controlling gas that produces uniform growth of the tungsten layer in a plurality of directions compared to a tungsten layer that is deposited using the source gas containing tungsten and the reducing gas, but without using the growth rate controlling gas.

Abstract translation: 使用含有钨，还原气体和含氮气体的源气体化学气相沉积钨或其它金属层。 与使用含有钨和还原气体的源气体进行化学气相沉积的钨层相比，含氮气体可以用作表面粗糙度降低气体，其降低钨层的粗糙度，但不使用表面粗糙度还原气体 。 以另一种方式看，与使用含钨和还原气体的源气体沉积的钨层相比，含氮气体充当生长速率控制气体，其产生钨层在多个方向上的均匀生长，但是 而不用生长速率控制气体。

公开(公告)号：US06174809B1

公开(公告)日：2001-01-16

申请号：US09212090

申请日：1998-12-15

Applicant: Sang-bom Kang ,  Yun-sook Chae ,  Chang-soo Park ,  Sang-in Lee

Inventor： Sang-bom Kang ,  Yun-sook Chae ,  Chang-soo Park ,  Sang-in Lee

IPC: H01L2144

CPC classification number: H01L21/76846 ,  C23C16/45561 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76843

Abstract: A method for forming a metal layer using an atomic layer deposition process. A sacrificial metal atomic layer is formed on a semiconductor substrate by reacting a precursor containing a metal with a reducing gas, and a metal atomic layer is formed of metal atoms separated from a metal halide gas on a semiconductor substrate by reacting the sacrificial metal atomic layer with a metal halide gas. Also, a silicon atomic layer may be additionally formed on the metal atomic layer using a silicon source gas, to thereby alternately stack metal atomic layers and silicon layers. Thus, a metal layer or a metal silicide layer having excellent step coverage can be formed on the semiconductor substrate.

Abstract translation: 一种使用原子层沉积工艺形成金属层的方法。 通过使包含金属的前体与还原气体反应而在半导体衬底上形成牺牲金属原子层，并且金属原子层由半导体衬底上的金属卤化物气体分离的金属原子形成，通过使牺牲金属原子层 与金属卤化物气体。 此外，可以使用硅源气体在金属原子层上另外形成硅原子层，从而交替堆叠金属原子层和硅层。 因此，可以在半导体衬底上形成具有优异的阶梯覆盖的金属层或金属硅化物层。

公开(公告)号：US6144060A

公开(公告)日：2000-11-07

申请号：US127353

申请日：1998-07-31

Applicant: In-seon Park ,  Yeong-kwan Kim ,  Sang-in Lee ,  Byung-hee Kim ,  Sang-min Lee ,  Chang-soo Park

Inventor： In-seon Park ,  Yeong-kwan Kim ,  Sang-in Lee ,  Byung-hee Kim ,  Sang-min Lee ,  Chang-soo Park

IPC: H01L21/8247 ,  H01L21/02 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L27/10852 ,  H01L28/55

Abstract: Integrated circuit devices include a first dielectric layer, an electrically insulating layer on the first dielectric layer and an an aluminum oxide buffer layer formed by atomic layer deposition (ALD) and stabilized by heat treatment at a temperature of less than about 600.degree. C., between the first dielectric layer and the electrically insulating layer. The first dielectric layer may comprise a high dielectric material such as a ferroelectric or paraelectric material. The electrically insulating layer may also comprise a material selected from the group consisting of silicon dioxide, borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). To provide a preferred integrated circuit capacitor, a substrate may be provided and an interlayer dielectric layer may be provided on the substrate. Here, a metal layer may also be provided between the interlayer dielectric layer and the first dielectric layer. The metal layer may comprise a material selected from the group consisting of Pt, Ru, Ir, and Pd.

Abstract translation: 集成电路器件包括第一电介质层，第一电介质层上的电绝缘层和通过原子层沉积（ALD）形成并通过在小于约600℃的温度下进行热处理而稳定的氧化铝缓冲层， 在第一介电层和电绝缘层之间。 第一电介质层可以包括高电介质材料，例如铁电或顺电材料。 电绝缘层还可以包括选自二氧化硅，硼磷硅酸盐玻璃（BPSG）和磷硅玻璃（PSG）的材料。 为了提供优选的集成电路电容器，可以提供衬底，并且可以在衬底上提供层间电介质层。 这里，还可以在层间介电层和第一介电层之间设置金属层。 金属层可以包括选自Pt，Ru，Ir和Pd的材料。

公开(公告)号：US6001683A

公开(公告)日：1999-12-14

申请号：US655122

申请日：1996-05-28

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/1052

Abstract: A method of forming an interconnection by using a landing pad is disclosed. In a semiconductor device having a memory cell portion and a peripheral circuit portion, a refractory metal is used for the bitline instead of the usual polycide, to concurrently form a contact on each active region of an N-type and a P-type, then a landing pad is formed on the peripheral circuit portion when a bitline is formed on the memory cell portion. In such a process, a substantial contact hole for the interconnection is formed on the landing pad so that an aspect ratio of the contact can be lowered. Accordingly, when forming a metal interconnection, the contact hole for the interconnection is easily filled by Al reflow so that the coverage-step of the metal being depositing in the contact hole for the interconnection is enhanced, the contact resistance is reduced. Further, the reliability of the semiconductor device is improved.

Abstract translation: 公开了一种通过使用着陆垫形成互连的方法。 在具有存储单元部分和外围电路部分的半导体器件中，难题金属用于位线而不是通常的多晶硅化物，以在N型和P型的每个有源区上同时形成接触，然后 当在存储单元部分上形成位线时，在外围电路部分上形成一个着陆焊盘。 在这种过程中，用于互连的实质接触孔形成在着陆焊盘上，使得可以降低接触的纵横比。 因此，当形成金属互连时，通过Al回流容易地填充用于互连的接触孔，使得在用于互连的接触孔中沉积的金属的覆盖阶梯增强，接触电阻降低。 此外，提高了半导体器件的可靠性。

公开(公告)号：US5869902A

公开(公告)日：1999-02-09

申请号：US612792

申请日：1996-03-11

Applicant: Sang-in Lee ,  Chang-soo Park

Inventor： Sang-in Lee ,  Chang-soo Park

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76865 ,  H01L21/3105 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via), a reactive spacer formed on the sidewall of the opening or a reactive layer formed on the sidewall and on the bottom surface of the opening and a first conductive layer formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer is formed on the sidewall of the opening, when the first conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer improves the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature. Thus, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 .mu.m in size and having an aspect ratio greater than 1.0, can be completely filled with Al, to thereby enhance the reliability of the wiring of a semiconductor device.

Abstract translation: 公开了具有新型接触结构的半导体器件的布线层。 半导体器件包括半导体衬底，具有开口（接触孔或通孔）的绝缘层，形成在开口的侧壁上的反应性间隔物或形成在开口的侧壁和底表面上的反应层，第一 形成在绝缘层上的完全填充开口的导电层。 由于反应性间隔物或层形成在开口的侧壁上，所以当沉积第一导电层材料时，将形成大的岛形成溅射的Al膜的大颗粒。 此外，提供反应间隔物或层在用于在低于熔融温度的高温下填充开口的热处理步骤期间改善了第一导电层的回流。 因此，可以确保用溅射的Al完全填充开口。 尺寸小于1μm并且具有大于1.0的纵横比的所有接触孔可以完全填充Al，从而提高半导体器件的布线的可靠性。

公开(公告)号：US5843842A

公开(公告)日：1998-12-01

申请号：US697880

申请日：1996-09-03

Applicant: Sang-in Lee ,  Jeong-in Hong ,  Jong-ho Park

Inventor： Sang-in Lee ,  Jeong-in Hong ,  Jong-ho Park

IPC: H01L23/52 ,  H01L21/027 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC classification number: H01L21/76843 ,  H01L21/0276 ,  H01L21/28512 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53271 ,  H01L2924/0002

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process. The semiconductor device preferably includes a diffusion barrier layer under the first conductive layer and on the semiconductor substrate, on the insulating layer, and on the inner surface of the opening which prevents a reaction between the first conductive layer and the semiconductor substrate or the insulating layer. A method for forming the wiring layer is also disclosed. Providing a semiconductor device with the wiring layer reduces the leakage current by preventing Al spiking. Since the first conductive layer undergoes a heat-treatment step at a temperature below the melting point, while flowing into the opening and completely filling it with the first conductive layer material, no void is formed in the opening. Good semiconductor device reliability is ensured in spite of the contact hole being less than 1 .mu.m in size and having an aspect ratio greater than 1.0.

Abstract translation: 公开了具有新型接触结构的半导体器件的布线层。 半导体器件包括半导体衬底，具有开口（接触孔）的绝缘层和形成在绝缘层上的完全填充开口的第一导电层。 在随后的用第一导电层材料填充开口的热处理步骤中，第一导电层不产生任何Si沉淀物。 半导体器件还可以包括在第一导电层上具有平坦化表面的第二导电层。 这改善了随后的光刻。 可以在第二导电层上形成抗反射层，以防止在光刻工艺期间不期望的反射。 半导体器件优选地包括在第一导电层下方，半导体衬底上的绝缘层上的扩散阻挡层，以及防止第一导电层与半导体衬底或绝缘层之间的反应的开口内表面 。 还公开了一种用于形成布线层的方法。 提供具有布线层的半导体器件通过防止Al尖峰来减少漏电流。 由于第一导电层在低于熔点的温度下经历热处理步骤，同时流入开口并用第一导电层材料完全填充，因此在开口中不形成空隙。 尽管接触孔的尺寸小于1μm，并且纵横比大于1.0，确保良好的半导体器件的可靠性。

公开(公告)号：US5665659A

公开(公告)日：1997-09-09

申请号：US257420

申请日：1994-06-09

Applicant: Sang-in Lee ,  Gil-heyun Choi ,  Young-soo Jeon

Inventor： Sang-in Lee ,  Gil-heyun Choi ,  Young-soo Jeon

IPC: H01L21/28 ,  C23C14/04 ,  C23C14/58 ,  H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  C23C14/34 ,  H01L21/324 ,  H01L21/44

CPC classification number: C23C14/5806 ,  C23C14/046 ,  H01L21/28512 ,  H01L21/321 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76877

Abstract: A method for forming a metal layer including the steps of heat treating a semiconductor substrate for a predetermined time at an intermediate temperature between 200.degree. C. and 400.degree. C., then depositing the metal layer on the semiconductor substrate at a temperature below 200.degree. C., in a vacuum, then thermally treating the metal layer at a temperature between 0.6 Tm-1.0 Tm (where Tm is the melting point of the metal layer), without breaking the vacuum, thereby reflowing the grains of the metal layer, and then gradually cooling the metal layer. Alternatively, the intermediate heat-treatment step can be performed after the metal layer is thermally treated, in which case, the metal layer should thereafter be rapidly cooled.

Abstract translation: 一种用于形成金属层的方法，包括以下步骤：在200℃至400℃的中间温度下将半导体衬底热处理预定时间，然后在低于200℃的温度下将金属层沉积在半导体衬底上 在真空中，然后在0.6Tm -1.0Tm（其中Tm是金属层的熔点）的温度下对金属层进行热处理，而不破坏真空，从而回流金属层的晶粒，以及 然后逐渐冷却金属层。 或者，中间热处理步骤可以在金属层被热处理之后进行，在这种情况下，金属层此后应该被快速冷却。

公开(公告)号：US5567987A

公开(公告)日：1996-10-22

申请号：US480975

申请日：1995-06-07

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L21/285 ,  H01L21/441 ,  H01L21/48 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/43

CPC classification number: H01L21/76838 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.

Abstract translation: 本发明涉及一种用于半导体器件的布线结构及其制造方法，其填充低于一半微米的接触孔。 在半导体衬底上形成绝缘层，并在绝缘层中形成接触孔。 在绝缘层上，通过CVD法沉积第一金属，以形成填充接触孔的CVD金属层或CVD金属塞。 然后，将如此获得的CVD金属层或CVD金属插塞在低于第一金属的熔点的高温下在真空中进行热处理，由此平坦化CVD金属层的表面。 通过溅射法在CVD金属层或CVD金属插塞上沉积第二种金属，从而形成溅射金属层。 通过CVD法将接触孔填充第一金属，然后通过溅射法沉积可靠的溅射金属层。 布线层可用于下一代的半导体器件。

公开(公告)号：US5552341A

公开(公告)日：1996-09-03

申请号：US164920

申请日：1993-12-10

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L21/28 ,  C23C14/06 ,  C23C14/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC classification number: H01L21/76856 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/532 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer. The diffusion barrier layer has a surface region provided with a silylation layer which is formed on the diffusion barrier layer by a plasma process using silicon hydride or by a reactive sputtering method using SiH.sub.4. When a metal layer is formed on the silylation layer, the wettability between the diffusion barrier layer and the metal is enhanced and large grains are formed, thereby increasing the step coverage for the contact hole of the metal layer or for the via hole. Additionally, when heat treatment is performed after the metal layer is formed on the silylation layer, the reflow characteristic of the metal layer becomes good, to thereby facilitate the filling of the contact hole or the via hole. When the wiring layer is thus formed, metal wiring having good reliability can be obtained and a subsequent scintering process is rendered unnecessary.

Abstract translation: 一种在半导体晶片上形成扩散阻挡层的半导体器件及其制造方法。 扩散阻挡层具有通过使用氢化硅的等离子体处理或通过使用SiH 4的反应溅射法形成在扩散阻挡层上的甲硅烷基层的表面区域。 当在甲硅烷基层上形成金属层时，扩散阻挡层和金属之间的润湿性增强，并且形成大的晶粒，从而增加金属层或通孔的接触孔的阶梯覆盖。 此外，当在甲硅烷基层上形成金属层之后进行热处理时，金属层的回流特性变好，从而有助于填充接触孔或通孔。 当这样形成布线层时，可以获得具有良好可靠性的金属布线，并且不需要随后的烧结处理。

公开(公告)号：US07052918B2

公开(公告)日：2006-05-30

申请号：US10410341

申请日：2003-04-10

Applicant: Jae-soon Lim ,  Yeong-kwan Kim ,  Heung-soo Park ,  Sang-in Lee

Inventor： Jae-soon Lim ,  Yeong-kwan Kim ,  Heung-soo Park ,  Sang-in Lee

IPC: H01L21/8242

CPC classification number: H01L28/40 ,  H01L21/3142 ,  H01L21/31604 ,  H01L21/31616

Abstract: A multi-layer film for a thin film structure, a capacitor using the multi-layer film and methods for fabricating the multi-layer film and the capacitor, the multi-layer film including a composition transition layer between a lower material layer and an upper material layer respectively formed of different elements whose interaction parameters are different from each other, the composition transition layer containing both elements of the lower and upper material layers, the concentration of the composition transition layer gradually varying from the portion of the composition transition layer contacting with the lower material layer to the portion of the composition transition layer contacting with the upper material layer such that the concentration of the element of the upper material layer is relatively large in its portion adjacent to the upper material layer, each of the lower and upper material layers being formed of an oxide or nitride material of aluminum, silicon, zirconium, cerium, titanium, yttrium, tantalum or niobium.