中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

61 records (took 0.038 seconds)

    Print-circuit board forming method and print-circuit board
    31.
    发明申请
    Print-circuit board forming method and print-circuit board 审中-公开
    印刷电路板成型方法和印刷电路板

    公开(公告)号：US20050109853A1

    公开(公告)日：2005-05-26

    申请号：US10986928

    申请日：2004-11-15

    Applicant: Satoshi Torii

    Inventor： Satoshi Torii

    IPC: H05K3/28 ,  G06K19/06 ,  H05K1/02 ,  H05K3/00

    CPC classification number: G06K19/06009 ,  H05K1/0266 ,  H05K3/28 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/099

    Abstract: It is an object to form different identifying marks without using a lot of pattern forming plates for forming identifying marks, while forming identifying marks on print-circuit boards. A print-circuit board 5 which has a conductor layer 2 and a resist layer 3 is formed by the first step of forming patterns composing identifying marks on the conductor layer 2 and the second step of forming patterns composing identifying marks on the resist layer 3. At the first step, the patterns having patterns 2a and 2b are formed on the conductor layer 2. At the second step, the patterns having patterns 3a, 3b, 3c and 3d are formed on the resist layer 3. The patterns 2a and 3a and the patterns 2b and 3c compose one identifying mark for identifying the print-circuit board 5. Another patterns 3b and 3d are also formed on the resist layer. The patterns 3b and 3d are formed as patterns for composing the other identifying mark.

    Abstract translation: 本发明的目的是在印刷电路板上形成识别标记的同时形成识别标记，而不需要大量图案形成板来形成不同的识别标记。 通过在导体层2上形成构成识别标记的图案的第一步骤和在抗蚀剂层3上形成构成识别标记的图案的第二步骤，形成具有导体层2和抗蚀剂层3的印刷电路板5。 在第一步骤中，在导体层2上形成具有图案2a和2b的图案。在第二步骤中，在抗蚀剂层3上形成具有图案3a，3b，3c和3d的图案。 图案2a和3a以及图案2b和3c构成用于识别印刷电路板5的一个识别标记。在抗蚀剂层上也形成另一图案3b和3d。 图案3b和3d形成为用于构成另一识别标记的图案。

    Nonvolatile semiconductor memory device and erasing method of nonvolatile semiconductor memory device
    32.
    发明授权
    Nonvolatile semiconductor memory device and erasing method of nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件和非易失性半导体存储器件的擦除方法

    公开(公告)号：US08649226B2

    公开(公告)日：2014-02-11

    申请号：US13479620

    申请日：2012-05-24

    Applicant: Satoshi Torii

    Inventor： Satoshi Torii

    IPC: G11C11/34

    CPC classification number: G11C16/14 ,  H01L21/823462 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546

    Abstract: A nonvolatile semiconductor memory device including a first bit line commonly coupling drain sides memory cells; a word line commonly coupling control gates of memory cell transistors; a column decoder coupled to a second bit line; a row decoder coupled to a word line; a first transistor having a source coupled to the first bit line and having a drain electrically coupled to the column decoder via the second bit line; and a first control unit for controlling potential of a gate of the first transistor, the memory cell transistor being formed over a first well, the first transistor being formed over a second well electrically isolated from the first well, a film thickness of a gate insulation film of the first transistor being smaller than that of a gate insulation film of a second transistor formed in the row decoder and coupled to the word line.

    Abstract translation: 一种非易失性半导体存储器件，包括通常耦合漏极侧存储单元的第一位线; 通常耦合存储单元晶体管的控制栅极的字线; 耦合到第二位线的列解码器; 耦合到字线的行解码器; 第一晶体管，具有耦合到第一位线的源极，并且具有经由第二位线电耦合到列解码器的漏极; 以及第一控制单元，用于控制所述第一晶体管的栅极的电位，所述存储单元晶体管形成在第一阱上，所述第一晶体管形成在与所述第一阱电隔离的第二阱上，栅极绝缘膜的膜厚度 第一晶体管的膜比在行解码器中形成的第二晶体管的栅极绝缘膜的膜薄，并且耦合到字线。

    SONOS memory with inversion bit-lines
    36.
    发明申请
    SONOS memory with inversion bit-lines 有权
    具有反转位线的SONOS存储器

    公开(公告)号：US20070058442A1

    公开(公告)日：2007-03-15

    申请号：US11595639

    申请日：2006-11-10

    Applicant: Hidehiko Shiraiwa ,  Jaeyong Park ,  Satoshi Torii ,  Hideki Arakawa ,  Masaru Yano

    Inventor： Hidehiko Shiraiwa ,  Jaeyong Park ,  Satoshi Torii ,  Hideki Arakawa ,  Masaru Yano

    IPC: G11C16/04

    CPC classification number: H01L29/792 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

    Abstract: A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

    Abstract translation: 形成在半导体衬底内的SONOS存储单元包括设置在半导体衬底上的底部电介质，设置在底部电介质上的电荷捕获材料和设置在电荷俘获材料上的顶部电介质。 此外，SONOS存储单元包括设置在顶部电介质上的字线栅极结构和用于在半导体衬底内引入至少一个反转位线的至少一个位线栅极。

    Recessed channel with separated ONO memory device
    38.
    发明授权
    Recessed channel with separated ONO memory device 有权
    嵌入式通道具有分离的ONO存储器件

    公开(公告)号：US07067377B1

    公开(公告)日：2006-06-27

    申请号：US10812703

    申请日：2004-03-30

    Applicant: Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii ,  Mark T. Ramsbey

    Inventor： Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii ,  Mark T. Ramsbey

    IPC: H01L21/336

    CPC classification number: H01L29/42352 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

    Abstract: Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.

    Abstract translation: 提供了制造具有凹陷通道和分段/分离的ONO层的U形存储器件的系统和方法。 通过分离的ONO层促进多位操作，该ONO层包括邻近源极/漏极区的多晶硅栅极结构的侧壁上的电荷俘获区域。 存储器单元的编程和擦除由于作用源极区域和栅极之间的距离相对较短而便于实现。 此外，通过在凹陷多晶硅栅极周围移动的相对较长的U形沟道区域减轻了短沟道效应，从而增加了沟道长度的深度尺寸。

    Memory device with barrier layer
    39.
    发明授权
    Memory device with barrier layer 有权
    具有阻挡层的存储器件

    公开(公告)号：US07053445B1

    公开(公告)日：2006-05-30

    申请号：US11194471

    申请日：2005-08-02

    Applicant: Youseok Suh ,  Satoshi Torii ,  Lei Xue

    Inventor： Youseok Suh ,  Satoshi Torii ,  Lei Xue

    IPC: H01L29/788

    CPC classification number: H01L29/7881 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

    Abstract: A memory device may include a substrate, a dielectric layer formed on the substrate and a charge storage element formed on the dielectric layer. The memory device may also include an inter-gate dielectric formed on the charge storage element, a barrier layer formed on the inter-gate dielectric and a control gate formed on the barrier layer. The barrier layer prevents reaction between the control gate and the inter-gate dielectric.

    Abstract translation: 存储器件可以包括衬底，形成在衬底上的电介质层和形成在电介质层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的栅极间电介质，形成在栅极间电介质上的阻挡层和形成在阻挡层上的控制栅极。 阻挡层防止控制栅极和栅极间电介质之间的反应。

    Printed circuit board and structure for soldering electronic parts thereto
    40.
    发明授权
    Printed circuit board and structure for soldering electronic parts thereto 失效
    印刷电路板和用于将电子部件焊接到其上的结构

    公开(公告)号：US07009117B2

    公开(公告)日：2006-03-07

    申请号：US10618593

    申请日：2003-07-15

    Applicant: Satoshi Torii

    Inventor： Satoshi Torii

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H05K3/306 ,  H05K3/3447 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10651 ,  H05K2201/2036 ,  H05K2203/1178

    Abstract: A printed circuit board, which is guaranteed to be free of defective soldering in mounting and connecting electric or electronic parts or devices to the printed circuit, has a circuit pattern printed on its substrate, and an anti-soldering layer is laid on the circuit pattern to prevent soldering material from sticking to the circuit pattern and silk-screen printing areas are laid on the anti-soldering layer to indicate where selected electric or electronic parts or devices are to be mounted. Each silk-screen printing area has terminal holes made therein. The board has a substrate-exposed zone traversing the silk-screen printing area to leave its opposite extensions open to the surrounding atmosphere, thereby allowing heated air and gases to escape from the interspace between the bottom of the electric or electronic part or device and the exposed substrate.

    Abstract translation: 保证在电气或电子部件或设备安装和连接到印刷电路上无缺陷焊接的印刷电路板具有印刷在其基板上的电路图案，并且将抗焊层铺设在电路图案上 为了防止焊接材料粘附到电路图案上，并且丝网印刷区域铺设在防焊层上，以指示所选择的电气或电子部件或装置将要安装在哪里。 每个丝网印刷区域都具有端子孔。 该板具有穿过丝网印刷区域的基板暴露区域，以使其相对的延伸部向周围的大气开放，从而允许加热的空气和气体从电气或电子部件或装置的底部与 曝光底物。

Patent Agency Ranking