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42 条记录 (耗时 0.016 秒)

    Partial local self-boosting of a memory cell channel
    1.
    发明授权
    Partial local self-boosting of a memory cell channel 有权
    部分局部自增强的存储单元通道

    公开(公告)号：US07848146B2

    公开(公告)日：2010-12-07

    申请号：US12407228

    申请日：2009-03-19

    申请人： Youseok Suh ,  Ya-Fen Lin ,  Coling Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

    发明人： Youseok Suh ,  Ya-Fen Lin ,  Coling Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

    摘要翻译： 公开了一种用于存储器单元通道的局部局部自升压的方法。 作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于 将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。 此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压 程序的漏极侧禁止存储单元关闭。 在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
    3.
    发明申请
    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
    通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀

    公开(公告)号：US20080171416A1

    公开(公告)日：2008-07-17

    申请号：US11653649

    申请日：2007-01-12

    申请人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    发明人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

    摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

    Flash memory cell with a flair gate
    5.
    发明授权
    Flash memory cell with a flair gate 有权
    闪存单元，带有风格门

    公开(公告)号：US08367537B2

    公开(公告)日：2013-02-05

    申请号：US11801823

    申请日：2007-05-10

    申请人： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    发明人： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    IPC分类号： H01L21/283

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

    摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

    摘要翻译： 本发明的实施例涉及一种形成存储单元的方法。 该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。 与STI区域接触的衬底的有源区域的一部分形成位线STI边缘。 该方法还包括在衬底的有源区上方和STI区上形成栅极结构。 栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。

    Apparatus and method for extended nitride layer in a flash memory
    6.
    发明授权
    Apparatus and method for extended nitride layer in a flash memory 有权
    闪存中的延伸氮化物层的装置和方法

    公开(公告)号：US08208296B2

    公开(公告)日：2012-06-26

    申请号：US12706710

    申请日：2010-02-16

    申请人： Timothy Thurgate ,  Shenqing Fang ,  Kuo Tung Chang ,  Youseok Suh

    发明人： Timothy Thurgate ,  Shenqing Fang ,  Kuo Tung Chang ,  Youseok Suh

    IPC分类号： G11C11/34

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833

    摘要： A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.

    摘要翻译： 提供了一种用于存储信息的方法和装置。 存储器的核心区域包括半导体层，至少一个浅沟槽，绝缘体和电荷俘获层。 半导体层包括至少一个源极/漏极区域，以及设置在源极/漏极区域上方的绝缘体。 电荷捕获层在绝缘体内，并且电荷捕获层高于源/漏区的整个宽度，并且延伸超过源极/漏极区的宽度至少一埃，使得电荷捕获层 延伸到至少一个浅沟槽中。

    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
    7.
    发明授权
    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
    通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀

    公开(公告)号：US07803680B2

    公开(公告)日：2010-09-28

    申请号：US11653649

    申请日：2007-01-12

    申请人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    发明人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

    摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

    Memory Device with Barrier Layer
    8.
    发明申请
    Memory Device with Barrier Layer 有权
    具有阻隔层的存储器件

    公开(公告)号：US20080191269A1

    公开(公告)日：2008-08-14

    申请号：US11997464

    申请日：2006-07-21

    申请人： Youseok Suh ,  Satoshi Torii ,  Lei Xue

    发明人： Youseok Suh ,  Satoshi Torii ,  Lei Xue

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7881 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

    摘要： A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).

    摘要翻译： 存储器件（100）可以包括衬底（110），形成在衬底（110）上的电介质层（210）和形成在电介质层（210）上的电荷存储元件（220）。 存储器件（100）还可以包括形成在电荷存储元件（220）上的栅极间电介质（230），形成在栅极间电介质（230）上的阻挡层（240）和控制栅极（250） 形成在阻挡层（240）上。 阻挡层（240）防止控制栅极（250）和栅极间电介质（230）之间的反应。