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31.发明申请公开(公告)号：US20170125110A1
公开(公告)日：2017-05-04
申请号：US14928181
申请日：2015-10-30
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C2211/5634 , G11C2211/5641
Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with separate characterization on each side of a voltage distribution about a distribution mean. A read threshold voltage for a memory is adjusted by determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels and a distribution of data values read from cells using a plurality of read threshold voltages, wherein the statistical characteristics of the two adjacent memory levels are characterized independently on two sides about at least one mean of the statistical distribution; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage based on the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.
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32.发明申请公开(公告)号：US20170125089A1
公开(公告)日：2017-05-04
申请号：US14962538
申请日：2015-12-08
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C7/14 , G11C16/28 , G11C2211/5632 , G11C2211/5634
Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages; determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels, a distribution of data values read from one or more cells using a plurality of read threshold voltages and the gap; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage with the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.
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公开(公告)号：US09209835B2
公开(公告)日：2015-12-08
申请号：US14135837
申请日：2013-12-20
Applicant: Seagate Technology LLC
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C29/026 , G11C29/028 , G11C29/42 , G11C2029/4402 , H03M13/1117 , H03M13/1125
Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
Abstract translation: 用于读取非易失性存储器的装置包括跟踪模块，其可操作以计算非易失性存储器中的电压电平分布的平均值和方差，并且计算当基于所述非易失性存储器读取非易失性存储器时要使用的至少一个参考电压 平均值和方差，似然发生器可操作以计算在读取非易失性存储器时要使用的至少一个其它参考电压，其中至少一个其它参考电压至少部分地基于预定似然值星座，并且 将从非易失性存储器读取图案映射到似然值，以及读取控制器，其可操作以使用所述至少一个参考电压和所述至少一个其它参考电压来读取所述非易失性存储器以产生所述读取模式。
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公开(公告)号：US11042316B1
公开(公告)日：2021-06-22
申请号：US16564866
申请日：2019-09-09
Applicant: Seagate Technology LLC
Inventor： Hongmei Xie , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Alex Tang , Leonid Baryudin , Erich Franz Haratsch
IPC: G06F3/06
Abstract: A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.
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公开(公告)号：US10942655B2
公开(公告)日：2021-03-09
申请号：US16505909
申请日：2019-07-09
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Sundararajan Sankaranarayanan , Erich Franz Haratsch
IPC: G06F3/06
Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.
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Patent Agency Ranking
公开(公告)号：US10666295B1
公开(公告)日：2020-05-26
申请号：US16225272
申请日：2018-12-19
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.
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公开(公告)号：US10388385B2
公开(公告)日：2019-08-20
申请号：US15440225
申请日：2017-02-23
Applicant: Seagate Technology LLC
Inventor： Zhengang Chen , Erich F. Haratsch , Sundararajan Sankaranarayanan
Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.
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38.发明申请公开(公告)号：US20190130967A1
公开(公告)日：2019-05-02
申请号：US15799497
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
CPC classification number: G11C11/5642 , G11C7/04 , G11C11/5635 , G11C16/22 , G11C16/26 , G11C16/349 , G11C2211/5644
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
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公开(公告)号：US10263640B2
公开(公告)日：2019-04-16
申请号：US15478895
申请日：2017-04-04
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC: H03M13/11
Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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公开(公告)号：US20170125114A1
公开(公告)日：2017-05-04
申请号：US15205654
申请日：2016-07-08
Applicant: Seagate Technology LLC
Inventor： AbdelHakim S. Alhussien , Sundararajan Sankaranarayanan , Thuy Van Nguyen , Ludovic Danjean , Erich F. Haratsch
CPC classification number: G11C16/28 , G06F11/1012 , G11C11/5642 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page. (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.
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