公开(公告)号：US07053451B2

公开(公告)日：2006-05-30

申请号：US09988593

申请日：2001-11-20

申请人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/01

CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

摘要翻译： 在形成NMOS晶体管的源极/漏极区域的情况下，在N + +块区域中的N + +块区域<41>的栅极方向延伸区域 抗蚀剂膜<51>防止位于栅极方向延伸区域41a之下的阱区11注入N型杂质。 作为高电阻形成区域，其是具有在栅电极9的纵向延伸上注入N型杂质的可能性的阱区域11，可以形成为高电阻形成区域 比传统的高电阻形成区域窄。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。

公开(公告)号：US07005705B2

公开(公告)日：2006-02-28

申请号：US10261665

申请日：2002-10-02

申请人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

公开(公告)号：US20050218455A1

公开(公告)日：2005-10-06

申请号：US11067836

申请日：2005-02-28

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/0922 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US20050087779A1

公开(公告)日：2005-04-28

申请号：US10995193

申请日：2004-11-24

申请人： Shigenobu Maeda ,  Takashi Ipposhi ,  Yuuichi Hirano

发明人： Shigenobu Maeda ,  Takashi Ipposhi ,  Yuuichi Hirano

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/786 ,  H01L29/94 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/94

摘要： It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

摘要翻译： 本发明的目的是获得包括具有大Q值的电容的半导体器件。 在包括支撑衬底（165），掩埋氧化膜（166）和SOI层（171）的SOI衬底中，在SOI的上层部分中选择性地形成隔离氧化膜167（167a至167c） 层（171）与SOI层（171）的一部分保持为阱区（169）。 因此，获得隔离（部分隔离）结构。 在隔离氧化膜（167a）和（167b）之间的SOI层（171）中形成有N + +扩散区（168）和P + 区域（170）形成在隔离氧化膜（167b）和（167c）之间的SOI层（171）中。 因此，获得了具有设置在隔离氧化膜（167b）下面的P阱区域（169）的PN结表面的结型可变电容（C23）和N

公开(公告)号：US06538269B2

公开(公告)日：2003-03-25

申请号：US09906094

申请日：2001-07-17

申请人： Shigenobu Maeda

发明人： Shigenobu Maeda

IPC分类号： H01L2710

CPC分类号： H01L27/11807

摘要： In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

摘要翻译： 在栅极阵列中，通过根据栅极电极的材料将栅电极分成组来测量栅极长度，以区分这些组。 栅电极（4）的接触焊盘部（5）的形状根据组而不同。 这里描述的差异表现为例如通过扫描电子显微镜可区分的切口（6a-6c）或突起（6d-6f）的形状。

公开(公告)号：US06509211B2

公开(公告)日：2003-01-21

申请号：US09790699

申请日：2001-02-23

申请人： Yasuo Yamaguchi ,  Shigenobu Maeda ,  Iijong Kim

发明人： Yasuo Yamaguchi ,  Shigenobu Maeda ,  Iijong Kim

IPC分类号： H01L21339

CPC分类号： H01L29/78696 ,  H01L21/26506 ,  H01L21/26586 ,  H01L27/12 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78621

摘要： A semiconductor device having an SOI structure capable of effectively preventing diffusion of an impurity from a source/drain region on an endmost portion of a silicon layer under a gate electrode is disclosed. In this semiconductor device, nitrogen is introduced into at least either a source/drain region or an end portion of a semiconductor layer located under a gate electrode, and the concentration profile of the nitrogen has a first concentration peak at least in either one of an endmost portion of the source/drain region in the direction where the gate electrode extends and an endmost portion of the semiconductor layer located under the gate electrode. Due to this concentration profile of nitrogen, point defects or the like serving as mediation for diffusion of an impurity are trapped, whereby diffusion of the impurity from the source/drain region is inhibited as a result. Thus, generation of an abnormal leakage current or the like is prevented.

摘要翻译： 公开了一种具有SOI结构的半导体器件，该SOI结构能够有效地防止杂质从源极/漏极区域扩散到栅电极下方的硅层的最末端部分。 在该半导体器件中，将氮气引入位于栅电极下方的半导体层的源极/漏极区域或端部的至少一个中，并且氮的浓度分布至少具有第一浓度峰值 源极/漏极区域在栅电极延伸的方向的最末端部分和位于栅电极下方的半导体层的最末端部分。 由于氮的浓度分布，作为用于杂质扩散的介质的点缺陷等被捕获，结果导致杂质从源/漏区的扩散受到抑制。 因此，防止产生异常的漏电流等。

公开(公告)号：US06486513B1

公开(公告)日：2002-11-26

申请号：US09464436

申请日：1999-12-16

申请人： Takuji Matsumoto ,  Shigenobu Maeda

发明人： Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621

摘要： An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to reach the buried oxide film, so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.

摘要翻译： 在掩埋氧化膜中设置SOI层，在SOI层的上表面设置源极和漏极，使其不与埋入氧化物膜接触。 由源极，漏极和SOI层形成的耗尽层延伸以到达掩埋氧化物膜，因此寄生电容降低。 该结构实现了能够在低漏极电压下降低结电容的SOIMOS晶体管。

公开(公告)号：US06358815B2

公开(公告)日：2002-03-19

申请号：US09886031

申请日：2001-06-22

申请人： Shigenobu Maeda

发明人： Shigenobu Maeda

IPC分类号： H01L2176

CPC分类号： H01L29/66772 ,  H01L21/306 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/1079 ,  H01L29/78603 ,  Y10S438/96

摘要： A semiconductor device comprises a silicon region (1) of the first conductivity type, a porous silicon layer (2) formed inside the silicon region (1) as a buried layer and a source region (3a) and a drain region (4a) of the second conductivity type different from the first conductivity type selectively formed in an upper surface of the silicon region (1). Bottom surfaces of the source region (3a) and the drain region (4a) are located adjacently above an upper surface of the porous silicon layer (2). As a result, depletion layers (8) in pn junctions between the silicon region (1) and the bottom surfaces of the source region (3a) and the drain region (4a) reach the inside of the porous silicon layer (2). With this structure, a semiconductor device which achieves a faster operation and lower power consumption while ensuring stability in operation of a MOSFET and a method of manufacturing the same are provided.

摘要翻译： 半导体器件包括第一导电类型的硅区域（1），形成在作为掩埋层的硅区域（1）内的多孔硅层（2）和源极区域（3a）和漏极区域（4a） 不同于在硅区域（1）的上表面中选择性地形成的第一导电类型的第二导电类型。 源极区域（3a）和漏极区域（4a）的底表面邻近位于多孔硅层（2）的上表面上方。 结果，硅区域（1）和源极区域（3a）和漏极区域（4a）的底表面之间的pn结中的耗尽层（8）到达多孔硅层（2）的内部。 利用这种结构，提供了一种在确保MOSFET的操作中的稳定性的同时实现更快的操作和更低功耗的半导体器件及其制造方法。

公开(公告)号：US06300230B2

公开(公告)日：2001-10-09

申请号：US09741340

申请日：2000-12-21

申请人： Shigenobu Maeda

发明人： Shigenobu Maeda

IPC分类号： H01L2128

CPC分类号： H01L27/11807

摘要： In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

摘要翻译： 在栅极阵列中，通过根据栅极电极的材料将栅电极分成组来测量栅极长度，以区分这些组。 栅电极（4）的接触焊盘部（5）的形状根据组而不同。 这里描述的差异表现为例如通过扫描电子显微镜可区分的切口（6a-6c）或突起（6d-6f）的形状。

公开(公告)号：US06285072B1

公开(公告)日：2001-09-04

申请号：US09396358

申请日：1999-09-15

申请人： Shigenobu Maeda

发明人： Shigenobu Maeda

IPC分类号： H01L2906

CPC分类号： H01L29/66772 ,  H01L21/306 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/1079 ,  H01L29/78603 ,  Y10S438/96

摘要： A semiconductor device and a method of manufacturing the same are provided with a silicon region of a first conductivity type, a silicon layer including at least one cavity existing inside the silicon region as a buried layer, and a source/drain region of a second conductivity type different from the first conductivity type selectively formed directly on an upper surface of the silicon region with a bottom surface of the source/drain region located adjacent to an upper surface of the silicon layer such that a depletion layer between the silicon region and the bottom surface of the source/drain region exists inside the silicon layer. With such a structure, a semiconductor device achieves a faster operation and lower power consumption while ensuring stable operation as a MOSFET.

摘要翻译： 半导体器件及其制造方法设置有第一导电类型的硅区域，包括存在于硅区域内的至少一个空腔的硅层作为掩埋层，以及具有第二导电类型的源极/漏极区域 类型不同于直接在硅区的上表面上选择性地形成的第一导电类型，其中源极/漏极区的底表面邻近硅层的上表面，使得硅区和底部之间的耗尽层 源/漏区的表面存在于硅层的内部。 通过这样的结构，半导体器件实现更快的操作和更低的功耗，同时确保作为MOSFET的稳定操作。