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37 条记录 (耗时 0.026 秒)

    On-chip substrate bias generating circuit having substrate potential clamp and operating method therefor
    31.
    发明授权
    On-chip substrate bias generating circuit having substrate potential clamp and operating method therefor 失效
    具有衬底电位钳位的片上衬底偏置产生电路及其操作方法

    公开(公告)号：US4890011A

    公开(公告)日：1989-12-26

    申请号：US192576

    申请日：1988-05-11

    申请人： Hideshi Miyatake

    发明人： Hideshi Miyatake

    IPC分类号： G11C11/407 ,  G05F3/20 ,  G11C11/4074

    CPC分类号： G05F3/205 ,  G11C11/4074

    摘要： A semiconductor integrated circuit having a power supply terminal, ground terminal and a substrate bias terminal comprises a substrate voltage generating circuit connected to the power supply terminal and the ground terminal for generating a substrate bias voltage of a predetermined value and for applying the same to the substrate bias terminal, a MOS transistor provided between the substrate bias terminal and the ground terminal for bringing the substrate potential to the ground potential when the supply voltage of the power supply terminal exceeds a prescribed voltage value and a plurality of diode connected MOS transistors connected between the power supply terminal and the gate of the MOS transistor for deciding the prescribed voltage value.

    摘要翻译： 具有电源端子，接地端子和衬底偏置端子的半导体集成电路包括连接到电源端子和接地端子的衬底电压产生电路，用于产生预定值的衬底偏置电压并将其施加到 衬底偏置端子，设置在衬底偏置端子和接地端子之间的MOS晶体管，用于当电源端子的电源电压超过规定电压值时使衬底电位接地，并且多个二极管连接的MOS晶体管连接在 电源端子和用于决定规定电压值的MOS晶体管的栅极。

    Semiconductor memory device with active pull up
    34.
    发明授权
    Semiconductor memory device with active pull up 失效
    具有主动上拉功能的半导体存储器件

    公开(公告)号：US4809230A

    公开(公告)日：1989-02-28

    申请号：US938065

    申请日：1986-12-04

    申请人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    发明人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C11/4076 ,  G11C11/4094

    摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

    摘要翻译： MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。

    Dummy word line driving circuit for a MOS dynamic RAM
    35.
    发明授权
    Dummy word line driving circuit for a MOS dynamic RAM 失效
    用于MOS动态RAM的虚拟字线驱动电路

    公开(公告)号：US4757476A

    公开(公告)日：1988-07-12

    申请号：US876912

    申请日：1986-06-20

    申请人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    发明人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    IPC分类号： G11C11/401 ,  G11C7/14 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4099 ,  G11C7/02

    CPC分类号： G11C7/14 ,  G11C11/4099

    摘要： A dummy word line driving circuit for a MOS dynamic RAM comprises a dummy word line controller connected to each end of a pair of dummy word lines. A sub-decode signal which is opposite to the one inputted to a dummy word driver and a dummy set signal for writing a bit line information into a not-selected dummy cell are inputted to the dummy word line controller. Means for applying a dummy equalizing signal is connected to two full-sized dummy cells, for equalizing the two before the dummy word line is driven. The two full-sized dummy cells are equalized by the signal, resulting in a charge amount, which is to be a reference value, of a half of a full-sized memory cell.

    摘要翻译： 用于MOS动态RAM的虚拟字线驱动电路包括连接到一对虚拟字线的每一端的虚拟字线控制器。 将与输入到虚拟字驱动器的子解码信号相反的子解码信号和用于将位线信息写入未选择的虚拟单元的伪设置信号被输入到虚拟字线控制器。 用于应用虚拟均衡信号的装置连接到两个全尺寸的虚拟小区，用于在虚拟字线被驱动之前均衡两者。 两个全尺寸虚拟单元被信号相等，导致作为参考值的充电量为全尺寸存储单元的一半。